Current limit set in ADM1270

Hi,

Could you please provide feedback on the case. 

I am currently testing my board and stuck at this issue.

Please support.

Thanks,

Reshma.

Hi Reshma,

    Your description is missing a couple of key pieces of information. First, how much load capacitance are you driving? Second, what is the value of the capacitor on the TIMER pin?  Third, are you using any feedback around the FET, from gate to drain, to limit inrush current?

    The most likely reason for the issue is that you are attempting to start with the current at the (low) current limit, and this causes the TIMER pin to ramp up before VOUT = VIN. When the TIMER pin reaches 2V it turns off the FET. Since the current limit is low there is not enough time to bring up VOUT. When you raise the current limit it increases the VOUT ramp rate and allows VOUT to start before the TIMER pin reaches its threshold.

    You have several options:

1) Allow the increased value of ISET so that the current limit is large enough to reliably start the output before the TIMER pin reaches 2V. This requires you to check the SOA of the FET to ensure that it can handle the extra current.

2) Keep the ISET limit low, but increase the TIMER capacitor value. This requires you to check the SOA of the FET to ensure that it can handle the extra time under stress.

3) Add a Miller capacitor around the FET, from gate to drain to reduce inrush current below the current limit. This will maintain a safe inrush current during startup and prevent the TIMER pin from ramping up at all (you can take a long time to start safely). The value of the capacitor depends on the desired ramp rate of the output, which depends on the desired inrush current and the size of the load capacitor. You can find some helpful guidance in the LTC4250 datasheet, which talks about the capacitors around the FET on p8.

Hi Nenger ,

Thanks for the detailed explanation.

Please find the Design schematics for your review.

Changes made: The FLB pin is connected to source of the Q1 FET.

Please provide your comments on the design.

Thanks,

Reshma

Hi Nenger,

Please could you review the design scematics above and me know.

Also please provide the SPICE model for ADM1270

Thanks,

Reshma

Hi Reshma,

    Using a TIMER capacitor of 470pF gives a time-out of 47us. This is much too short to be useful.You need a longer time-out value, since it takes about 1ms to bring up the 10uF capacitor. In your testing when you changed the Vsense voltage to 50mV you also shortened the amount of time that it took to start the output, and this may have been sufficient to allow the output to start before the timer timed out. You would have to look at the VOUT and TIMER waveforms to observe this.

    In order to start the circuit with a 20mV Vsense limit you need to lengthen the timer to allow the circuit to reach VOUT=VIN before TIMER=2V. If it takes 1ms to start, then you need a capacitor > 10nF.

    Your chosen FET does not have an SOA plot, so we cannot estimate how long it can survive the stress of starting. We know from the datasheet that they do pulse testing at 12A and Vds=5V for 300us, so we can probably assume that a timer of 1ms is modestly safe here. You should contact your FET vendor to see if they can provide SOA information for this FET. Otherwise test it at maximum ambient temperature to make sure it survives startup.

Thanks!
  Nathan