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LTC3866 and LTC3851A, Question about external clock signal for synchronization


I have some questions about the external clock signal for synchronization to MODE/PLLIN pin.

I'm considering designing an external clock signal with frequency of 400kHz to 700kHz and ON time of 75ns to 500ns.

- Is there any problem with the ON time period? 

- Please let me know the specifications of the ON time.



Parents Reply
  • Hello Kazu,

    For the external clock signal driving the MODE/PLLIN pins of the LTC3866 and LTC3851A:

    • Keep the on-time and off-time greater than 100nsec.
    • The maximum allowable low clock level is 0.5V & the minimum allowable high clock level is 2.0V.
    • The high clock level should not exceed INTVCC and the low clock level should not go below -0.3V. These limits are the specified absolute maximum ratings for the pin on both parts.

    Best regards,


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