Hi,
I am planning to design a 2.5kW (84V 30A) PSFB converter (offline with Vin = 390V) for a battery charging solution. I have somewhat understood the ways by which this topology achieves ZVS and the significance of Leakage/shim inductance, Mosfet Coss, and deadtime in order to achieve this.
I am currently simulating this above application using LTC3722-1 and LTC3901. The values of the passive components like timing resistor, voltage dividers for fixed and adaptive delay programming, current sense, SBUS, UVLO, and timer (ltc3901), etc have been done as per the calculations in the datasheet. Some of the other values have been referenced from typical application design.
I have tried to design the transformer considering that Dmax ~ 70% and Dtyp ~ 65%. This yields a turn's ratio (Np/Ns) close to 3/1. The inductor ripple is set to 20% of the output current (i.e. 30A). I have got a magnetizing inductance value of 1.37 mH using the above parameters for an Fs of 100 kHz.
The simulation is working somewhat fine, however, the gate pulses of the LTC3901 don't look anywhere as close as expected (i.e. very short pulses). The output inductor (47uH) seems to go in DCM mode which I had assumed to be the main source of error of shortened gate pulses, as the ME+ may rise above ME- causing the termination of pulses. The SR mosfet dissipation is very high at almost 180 - 200 W during this scenario.
After changing the inductor value to around 111 uH and output cap to around 2000uF the DCM mode ceased to exist although there didn't seem to be any changes in the gate pulses. The mosfet dissipation improved somewhat to around 70 - 80W which is still quite high.
I feel like this case of high dissipation is mostly caused by the flow of forwarding current through body diode rather than the main channel of mosfet (due to gate turn off) or either reverse flow of current through body diode.
Note: I have changed the value of the sense resistor to 1m Ohm as that of the recommended value of 21.8 m Ohm considering Iprimary p-p to be around 13.59A. This was done due to IC terminating the gate pulses.
I am attaching the simulation for both the adaptive and the fixed delay one. I would really appreciate it if someone could shed some more light on this issue. Any help or suggestion is appreciated.
Regards,
Jonathan.
