I am designing a rather complex (for me!) system to power an FPGA and several other ICs. (Total of 11 voltages.) In order to simplify things as much as possible I used only modular components (LTM4644, LTM4623) and LDOs (LT3045, ADP7157). I hope that experienced designers out there can steer me away from making foolish mistakes in designing and implementing this system. I could find no general guidelines about this topic on the web. I am open to any advice you have based on your experiences.
I have studied the data sheets for these components as well as purchased demo boards for them. Studying the schematics and layout of the demo boards was very useful and triggered some of the questions that I am asking here.
General questions from a novice:
1 - Each power component datasheet specifies minimum input and output capacitance values to assure stability. Layout guidelines place these caps close to the input and output pins. Can I keep these values and placement when I piece together the circuit elements into the final circuit? Is there a concern about placing power components too close together - i.e will they interact? For example, a LT3045 powered from the output of the LTM4644; or multiple LT3045s powered from the same rail. Is there a some rule of thumb for spacing these apart?
2 - Some voltage rails (especially on the LDOs) will draw currents much less than the specified output of the component. As a safety measure, should I design in a load resistor to these rails that I can populate in case there are problems at low currents?
3 - I have demo boards for all of the different components and plan to link them together to partially model the system I am designing. (I will be able to produce 7 of the 11 rails.) They will be loaded so that the currents will be representative of the actual system. I can measure ripple and noise on the rails. A useful exercise?
As an additional complication, space (and other) limitations force me to place most of the power components on two mezzanine cards. For those who wish to look further into this I attached the power tree for the design. Base board (A) and two mezzanine boards (B,C) are identified in the drawing. (Clarification: FPGA mezzanine (B) is the mezzanine that powers the FPGA. The FPGA and all other non-power ICs are located on the base board (A).)
Questions:
4 - Do you see any issues in placing point-of-load power components on a mezzanine board?
5 - In the drawing I am using Samtec micro power connectors (UMP) to convey power to the baseboard that contains the FPGA and other components. But since the current per rail is less than 4A, I am considering using standard multi-pin board-to-board connectors (0.05" or 0.1" pitch) instead. Four or more pins would be assigned to each voltage (with an equal number of ground pins). If I go this way, is it better to tightly group the pins assigned to a voltage, or spread them across the connector?
6 - Should additional bulk capacitance be added on the base board for each voltage near the connector pins conveying the power? What capacitor value might I start with here?
Some more information about the system:
A regulated AC/DC switching power supply (120 mVpp) provides +12V and is connected to the board with a 3 foot, 14 gauge pair of wires (+12V, GND).
Multiple boards (initially 4) will be connected to the +12V supply in this fashion.
Three LT3045s on the base board generate +1.0V, +1.2V, and +1.8V for the single high-speed serial transceiver (MGT) of the Xilinx FPGA.
Four ADP7157s generate independent +1.2V outputs for two mixed signal ASICs (VMM).
I am using a PMBus power system manager (LTC2975) to control and monitor the voltages and currents of the four LTM4644 outputs. (I duplicated the circuits of the DC2428A demo board pair (DC2363A / DC2382A)).
Comments, warnings, suggestions would all be appreciated.
Thanks.
Ed
