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Power components together in a system

I am designing a rather complex (for me!) system to power an FPGA and several other ICs. (Total of 11 voltages.)  In order to simplify things as much as possible I used only modular components (LTM4644, LTM4623) and LDOs (LT3045, ADP7157).  I hope that experienced designers out there can steer me away from making foolish mistakes in designing and implementing this system.  I could find no general guidelines about this topic on the web.  I am open to any advice you have based on your experiences.

I have studied the data sheets for these components as well as purchased demo boards for them. Studying the schematics and layout of the demo boards was very useful and triggered some of the questions that I am asking here.

General questions from a novice:

1 - Each power component datasheet specifies minimum input and output capacitance values to assure stability.  Layout guidelines place these caps close to the input and output pins. Can I keep these values and placement when I piece together the circuit elements into the final circuit?  Is there a concern about placing power components too close together - i.e will they interact?  For example, a LT3045 powered from the output of the LTM4644; or multiple LT3045s powered from the same rail.  Is there a some rule of thumb for spacing these apart?

2 - Some voltage rails (especially on the LDOs) will draw currents much less than the specified output of the component.  As a safety measure, should I design in a load resistor to these rails that I can populate in case there are problems at low currents?

3 - I have demo boards for all of the different components and plan to link them together to partially model the system I am designing.  (I will be able to produce 7 of the 11 rails.)  They will be loaded so that the currents will be representative of the actual system.  I can measure ripple and noise on the rails.  A useful exercise?

As an additional complication, space (and other) limitations force me to place most of the power components on two mezzanine cards. For those who wish to look further into this I attached the power tree for the design.  Base board (A) and two mezzanine boards (B,C) are identified in the drawing.  (Clarification: FPGA mezzanine (B) is the mezzanine that powers the FPGA.  The FPGA and all other non-power ICs are located on the base board (A).)



4 - Do you see any issues in placing point-of-load power components on a mezzanine board?

5 - In the drawing I am using Samtec micro power connectors (UMP) to convey power to the baseboard that contains the FPGA and other components.  But since the current per rail is less than 4A, I am considering using standard multi-pin board-to-board connectors (0.05" or 0.1" pitch) instead.  Four or more pins would be assigned to each voltage (with an equal number of ground pins).  If I go this way, is it better to tightly group the pins assigned to a voltage, or spread them across the connector?

6 - Should additional bulk capacitance be added on the base board for each voltage near the connector pins conveying the power?  What capacitor value might I start with here?

Some more information about the system:

A regulated AC/DC switching power supply (120 mVpp) provides +12V and is connected to the board with a 3 foot, 14 gauge pair of wires (+12V, GND).
Multiple boards (initially 4) will be connected to the +12V supply in this fashion.

Three LT3045s on the base board generate +1.0V, +1.2V, and +1.8V for the single high-speed serial transceiver (MGT) of the Xilinx FPGA.

Four ADP7157s generate independent +1.2V outputs for two mixed signal ASICs (VMM).

I am using a PMBus power system manager (LTC2975) to control and monitor the voltages and currents of the four LTM4644 outputs. (I duplicated the circuits of the DC2428A demo board pair (DC2363A / DC2382A)).

Comments, warnings, suggestions would all be appreciated.


  • I'm not sure I can address your general questions other than suggesting that you start by creating a floorplan for your boards, i.e. decide where to place connectors, whether they are for power or plug in cards. Keep in mind any significant sources of heat generation, ease of plugging things in and out, etc.  As for how many board to board connectors, can the connector pass the max current and how much IR drop can you tolerate.  Long cables will have enough inductance that high di/dt could pose problems at powerup/down or hot plugging. 

    I designed the DC2428 board set and can answer specific questions you might have on those boards.


  • Thanks for taking the time to read my question. 

    Actually I have a few questions about the DC2428 board set.   When I compare the schematics in the Demo Manual of the DC2428A and the application information in the LTM4644 datasheet I notice some slight differences.  It involves connections when the power manager chip LTC2975 is used (p.32 LTM4644 datasheet).  The LTM4644 datasheet shows the 47uF capacitor installed after the 10m current sense resistor, while the demo board schematics shows it connected directly at the output pin (i.e. before the sense resistor).  Does this matter at all?  Also, on the demo board schematics there are additional 10nF filtering caps to GND on each of the current sense lines ISENSEP and ISENSEM (DC2382 schematic sheet 3).  Is this because of the long lines going between boards?  We are copying your demo board set schematic for our design.


  • The cap directly connected to the output serves to close the hot loop.  The cap after the sense resistor is meant to be a bulk cap, for lower freq. and can be higher ESR. 

    The 10nF cap on the Isense pins is for differential noise. The other 2 caps (to GND) provide filtering for common mode noise. The Isense lines are routed close together to minimize common mode noise. The filtering that you will need depends on many factors, including the noise profile at each node of the Rsense, the surrounding layout, routing lengths, and your accuracy needs under light vs heavy load conditions. However in this case, the noise developed across Rsense will be much lower than inductor DCR sensing which has a switch node that needs heavy filtering.  You might want to add the common mode caps as an option, but I think you'll find that the one cap is adequate.


  • Thanks.  I have a few more questions about the DC2428 board set.

    The 4 input caps of the LTM4644 are 22uF ceramic.  Two are 1210 and two are 1206.  Is there some subtle reason for using different packages?

    The demo board uses resistor arrays (pair) for the current sensing of the LTM4644 outputs.  Even though they have a 5% tolerance, the difference in values of the resistors in a pair should be much smaller because they are processed as a unit.  Is having the same resistance in each line the reason you chose to use arrays?

  • The input caps could have been 1210 for all. I don't recall why 2 of them were 1206. 

    For the resistor arrays, yes I chose them since they will likely match closer than two discrete resistors. The matching is important to keep the IR drop of each low and therefore the differential voltage as low as possible, yet still provide some noise filtering.  Each ISENSE pin draws some current, so resistor matching reduces this source of error/offset.


  • Thanks for taking the time to answer my questions about the DC2428 demo board set you designed.  I am basically copying it for my design.  I have a few more questions.  Please answer at your convenience.

    I noticed you used a diode-connected transistor (Q1) as the default temperature sensor rather than the internal diode of the LTM4644 (since R52 is not installed).  Is there a reason for this?  I believe I can directly connect the TEMP pin of the LTM4644 to the TSENSE0 pin of the LTC2975 and drop Q1.  Naming this net TSENSE0P, I should route AGND of the LTM4644 as a trace (TSENSE0M) to the LTC2975 where I couple TSENSE0P & TSENSE0M with a 0.1uF cap, while tying TSENSE0M to GND at the LTC2975.  (See p.26 top of schematic sheet in DC2428 demo board manual.)  Please confirm that I understand this correctly.

    Also I see an optional resistor R50 connecting GDN and AGND at the LTM4644 chip.  Why would that be installed?

  • I found it was difficult to sense a gnd connection that wasn't carrying current. It's best to make sense connections as if they are differential signals, so I chose to place an external diode-connected transistor in a location of my choosing.  It gave me flexibility. The TSENSEP and TSENSEM nets are defined at the board connectors, and in your design, I suggest treating the signals as a diff pair. The signal that the ADC measures is quite small, ~70mV.

    R50 was used to tie grounds together.  I put this option in the prototype and may have forgotten to remove it. I didn't see significant differences between the options.


  • So I will directly connect the TSENSEP net to the TEMP pin of the LTM4644 and not use Q1.  Is the linearity of the internal diode as good as that of the external diode-connected transistor Q1?  Is there a calibration for the internal diode?

  • Yes, you can wire Tsensep to the TEMP pin.  I just tested and measured the board with the internal diode. The 2975 measures 50C and my IR imager measures 47C.  But the imager can only read the top surface of the uModule.  When I used the external transistor, the 2975 measures 40C.  This is due to the fact that the ext transistor is mounted on the backside of the pcb.  So this is not surprising.

    Regarding calibration, I adjusted the MFR_TEMP_OFFSET parameter to account for the slight over temp reading.  I changed the value from the default zero setting to -3C.  This value can be saved to EEPROM.


  • Thank you for going beyond the call of duty here and making those measurements.  I am glad that I chose Analog Devices parts for my design.