ADM7151 Adjusting output voltage response time not consistent

Hi Chenxi,

What you're seeing is a byproduct of the low noise architecture of the LDO. Applying DAC to change voltage is valid but the delay in settling time is present. When you apply small changes on the REF_SENSE, that translates to a small differential voltage on the input of the OTA, and further translates to a small change in current on the OTA output (BYP; final stage of the reference voltage setting). This leads to large slew rate and high impedance on the BYP pin. 

Regarding LTspice, since modelling targets normal mode operation or behavior, this occurrence is not modelled exactly due to limitations.

Hope this helps.

Regards,

Bryan

Hi Chenxi,

What you're seeing is a byproduct of the low noise architecture of the LDO. Applying DAC to change voltage is valid but the delay in settling time is present. When you apply small changes on the REF_SENSE, that translates to a small differential voltage on the input of the OTA, and further translates to a small change in current on the OTA output (BYP; final stage of the reference voltage setting). This leads to large slew rate and high impedance on the BYP pin. 

Regarding LTspice, since modelling targets normal mode operation or behavior, this occurrence is not modelled exactly due to limitations.

Hope this helps.

Regards,

Bryan

Additionally, you can probe BYP and REF pins to verify the delay happening on those pins as well, meaning it follows the same delay caused by this DAC alteration.

Regards,

Bryan