# LTC4368 Over Current

Hello,

I'm using the LTC4368 for over current protection on a radio power supply.  The over current seems to be triggering during boot up and I'm not sure why.  I'm using a 7mOhm (1206) sense resistor for a 7A current limit.  The current readings I'm taking do not exceed 4A.  In the attached scope shot the yellow trace is taken at TP2 in the schematic and the blue trace is the retry pin.  I'm powering the circuit using a power analyzer at TP1, yellow trace is the input current.  The scope is triggered when the circuit is powered on.  The OC is tripped for two retry cycles and then allows the circuit to turn on.  Any thoughts as to what might be causing this?

Schematic

Scope

Power Analyzer

Parents
• Is there any output capacitance on TP2? How much?

What kind of load is on TP2? Does it turn on and draw current while the output cap is charging?

Also, I don't think D1 is necessary. Q1A already blocks reverse current.

-Aaron

• Hi Arron,

TP2 goes to an external connector which powers a radio.  The input capacitance of that device looks to be around 100uF from measurements.  There are no output caps on TP2.

Agreed, D1 is not necessary.  I'll be removing that on the next build.

Alex

• TP2 goes to an external connector which powers a radio.  The input capacitance of that device looks to be around 100uF from measurements.  There are no output caps on TP2

Ok, we'll say output capacitance is 100uF.

Where:
IGATE,TYP=35uA
CGATE=27pF

The calculated inrush is 130A!
We need to select an inrush lower than your 7A limit, and also low enough so the FET survives start-up.

Looking at the AOSD62666E's SOA curve:

Looking at the 10ms curve, we can see the FET can handle 12V, at 2A, for 10ms. Given that CLOAD is charging, VDS is not a constant 12V, so the FET only sees half this stress. Let’s target 1A of inrush for additional margin.

If we use a CGATE of 3.6nF, the inrush current range should be: 505mA (min), 972mA (typ), and 1.9A (max).

Make sure the RETRY pin no longer shows a cooldown cycle during start-up.
Then verify that ~1A of inrush current charges the output capacitance to 12V in 1.2ms.

-Aaron

• I see, I misread the datasheet on that.  I was thinking that Cgate limits the allowable inrush.  I adjusted C1 to 3.3nF and still get the same results.  The output capacitance is charging over 1.8ms, and I'm getting an inrush of around 1.5A.  So it looks like the output capacitance might be closer to 150uF.

Below is a scope shot of the first fault occurrence with differential probes on pins 8 and 9 of LTC4368.  TP1 was getting rather close to the UV limit of 10V so I adjusted it to 8V.  The schematic changes I've made for these measurements are:

R3 = 0

R6 = 4.75M

R7 = 232k

R8 = 75k

C1 = 3.3nF

-Alex

• My mistake, I did not update the schematic picture.

• I see, I misread the datasheet on that.  I was thinking that Cgate limits the allowable inrush.

Sizing CGATE with respect to CLOAD controls the inrush. A fixed 35uA charges CGATE, and OUT follows GATE since circuit is a common drain topology.

I adjusted C1 to 3.3nF and still get the same results.  The output capacitance is charging over 1.8ms, and I'm getting an inrush of around 1.5A.

I thought your previous result was IINRUSH>7A, which was tripping the circuit breaker and causing a retry cooldown cycle.

If IINRUSH=1.5A, then you shouldn’t have an overcurrent condition, so retry cycle should be gone.

Looking at scopeshot 1, TP1 or IN, ramps up from 0V to 12V, but then collapses for some reason. TP2 or OUT, is 12VDC, as if the output capacitance had previously been turned on, and is still holding its charge.

Moving on to scopeshot 2, TP1 or IN, holds at 9VDC, before randomly dropping out again.

What circuitry is upstream of TP1? It seems like the power source is collapsing, which trips the UV threshold on the 4368, causing FAULT# to go low.

I simulated your circuit, and it works normally. About 1.2A of inrush for 1.6ms.

Sim file is attached.
4368-2 EZ inrush 9-21-21.asc

-Aaron

• I see, I misread the datasheet on that.  I was thinking that Cgate limits the allowable inrush.

Sizing CGATE with respect to CLOAD controls the inrush. A fixed 35uA charges CGATE, and OUT follows GATE since circuit is a common drain topology.

I adjusted C1 to 3.3nF and still get the same results.  The output capacitance is charging over 1.8ms, and I'm getting an inrush of around 1.5A.

I thought your previous result was IINRUSH>7A, which was tripping the circuit breaker and causing a retry cooldown cycle.

If IINRUSH=1.5A, then you shouldn’t have an overcurrent condition, so retry cycle should be gone.

Looking at scopeshot 1, TP1 or IN, ramps up from 0V to 12V, but then collapses for some reason. TP2 or OUT, is 12VDC, as if the output capacitance had previously been turned on, and is still holding its charge.

Moving on to scopeshot 2, TP1 or IN, holds at 9VDC, before randomly dropping out again.

What circuitry is upstream of TP1? It seems like the power source is collapsing, which trips the UV threshold on the 4368, causing FAULT# to go low.

I simulated your circuit, and it works normally. About 1.2A of inrush for 1.6ms.

Sim file is attached.
4368-2 EZ inrush 9-21-21.asc

-Aaron

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