LT8641 Bottom Power NMOS Current Limit

Hi paulaei,

We only have the range that you see in the electrical characteristics table that should include variation in temperature. Bottom FET current limit is usually not a concern because this is usually not tripped in most applications especially if you have designed the right external components including inductance value. You can double check your design and current through this FET using LTspice.

Can you explain why the bottom power NMOS current limit is NOT the dominant term even though it is less than the top power NMOS current limit?
I have the same concern.
If I simulate the regulator, then it limits at 4A which is closer to the bottom power NMOS current limit (not the top).
Simulation is from Analog website: "LT8641 Demo Circuit - 2MHz µPower Ultralow EMI Buck Converter (5.5-65V to 5V @ 3.5A)"
Change load from 1.4Ω to 1Ω and see that it isn't capable of the datasheet's "5A Peak" specification and limits at 4A instead.

Can you explain why the bottom power NMOS current limit is NOT the dominant term even though it is less than the top power NMOS current limit?
I have the same concern.
If I simulate the regulator, then it limits at 4A which is closer to the bottom power NMOS current limit (not the top).
Simulation is from Analog website: "LT8641 Demo Circuit - 2MHz µPower Ultralow EMI Buck Converter (5.5-65V to 5V @ 3.5A)"
Change load from 1.4Ω to 1Ω and see that it isn't capable of the datasheet's "5A Peak" specification and limits at 4A instead.