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LT4294 Does not switch to Auxiliary input with TP-Link PSE.

Hi Engineer Zone Team

We are currently evaluating the LT4294 PD interface controller.
Please refer the attached schematic sheet titled “LT4294_PoE_Aux.pdf”.
Note only the essential circuitry is shown for clarity.

The intended maximum power required is between 7.5W and 10W and hence IEEE standard is adequate for the application.
In addition to the PoE there will be also an auxiliary voltage input with the following range.
10V <= Auxiliary Input Volage <= 48V.
The AUX pin threshold of the LT4294 is set by the resistive divider comprising of R19, R31 & R35.
Based on the resistor values shown, Vauxon = 10V and Vauxoff = 9.75V.

Test results and issues encountered.
1.    The system powers up when PoE is the only source of power, (Aux disconnected).
2.    The system powers up when Auxiliary input is the only source of power and above 10V,
(PoE disconnected).
3.    When both PoE and auxiliary input are available and with auxiliary input = 0V, the system is powered by PoE.
4.    As the auxiliary input voltage is increased above 10V PoE disconnects and auxiliary input becomes the source of power.

The LT4294 functions as expected in the above mentioned four cases.

But when operating as mentioned in case 4 and if the auxiliary input is reduced below the designed Vauxoff of 9.75V the LT4294 fails to connect to the PoE until the auxiliary input it is approximately below 5V.
This is only evident in one of the PSE namely the TP-Link P/N - TL-SG1016PE.

I have tested the above mentioned with two other PSE, listed below, and the LT4294 switched as expected.
Pro Elec Wall mount P/N - 28-21720.
Digitech P/N – YN-8040.

The measured voltage at AUX, pin 2, is 5.65V when Auxiliary Input Volage = 9V.
Since this is well below the Aux Pin threshold of 6.3V it is expected that the LT4294 will switch to the PoE.

Further Comments.

The gate and source voltages of the N-Channel MOSFET are equal and approximately at 8.48V (9V minus one diode drop across D2) implying that the MOSFET Q3 is off as Vgs = 0V. I would expect this since the internal charge pump is off and the internal Zener diode will make these potentials equal.
Also, the voltage at the net labelled “PoE+” is at about 8V. This also expected due to the body diode of the MSFET Q3. I would think this will not interfere with PSE detection offset voltage since it is after the PoE RJ45 in-built diodes and not visible at the PSE power interface.
The RJ45 connector used in the application is from Pulse Electronics P/N JXD0-0010NL, please refer the attached data sheet.

I would greatly appreciate your advice in solving the above issue.



  • Hello Diva,

    You are correct about the body diode causing the auxiliary voltage to appear at VPORT pin or POE+ on your schematic. The PSE should be looking for a valid PD, and the first step in the process is Detection. This occurs below 10V, with the PSE probing the PD with either a current or voltage, then doing a second measurement. This allows the PSE to measure the dV/dI slope to identify the 25k detection signature. An example from an ADI PSE's datasheet is shown below.

    The 8V at VPORT is going to reverse bias the diode bridge for any voltage less than ~8.7V, so it will look like high impedance to anything looking into the RJ45 port. The auxiliary voltage must drop low enough to not interfere with the PSE's detection. You could also consider an blocking diode if you need to operate with ~8V at the auxiliary.

    Best Regards,


  • Hi Eric

    Thanks a lot for the reply and it explains the problem.

    I have asked a general question regarding the power supply for the PD controller during the detection process under the title "Questions regarding the PoE PD controllers in general" just prior to posting the question you answered.

    It would be great if you could answer that also.