LTC3260
Recommended for New Designs
The LTC3260 is a low noise dual polarity output power supply that includes an inverting charge pump with both positive and negative LDO regulators. The...
Datasheet
LTC3260 on Analog.com
AD7124-8
Recommended for New Designs
The AD7124-8 is a low power, low noise, completely integrated
analog front end for high precision measurement applications. The
AD7124-8 W grade is AEC...
Datasheet
AD7124-8 on Analog.com
LTC3206
Production
The LTC3206 is a highly integrated multidisplay LED controller. The part contains a high efficiency, low noise fractional step-up/direct-connect charge...
Datasheet
LTC3206 on Analog.com
Hi,
I'm using a LTC3260 with a 5V input and ±1.8V output to give power to an AD7124-8. When I use a linear power supply with the pair LM317/LM337 there are no problem, but since I use the LTC3260 the values obtained from de ADC are erratic (it gives any value between both upper and lower limits). It seems to be noise from the LTC3206 but I can't find a special big noise. Any recommendation? The layout on th PCB of the LTC3260 part is very similar to the recommended at hte datasheet and the values of capacitors maybe a little higher (10uF replace all 1uF or 4.7uF marked at the datasheet) but all of less tha 1 uF are 10nF or 0.1 uF as in the datasheet. I placed a 10pF between ADJ- and LDO- and the Mode and RT pins are grounded. There is a less noisy IC for a better supply to a an ADC?
Thanks
Hi,
Thanks for your answer. Here it is the circuit. Output is ±1.8V and input 5.0V supplied by the 3.3V to 5.0V DC/DC converter.
Hi,
I've changed C26 to 1uF but there are no significant changes. The opposite plane of the PCB is GND. I do attach a picture that shows how close are the components and how is noise view on oscilloscope. X its1uS every mark and Y its 2 mV between marks so noise is 4.1 mVpp and a period of 2 uS (500 KHz). Noise is measured without any charge at outputs.
Hello,
Thank you for the pictures and info. One thing that is not as clear from the picture and the recommended layout below is the is the GNDing. It is essential that there is a good GND connections from CIN, COUT, and the LDO output capacitors. On the recommended layout there is a solid GND plane on layer two and plenty of GND vias to the IC EPAD to each capacitor. The capacitors should be as close to the part as possible and where possible the copper supplying the power to the caps should be as big as possible to reduce the inductance and resistance to the caps. The added impedance will create larger ripple on the output. In the picture the traces to the output caps look very thin and GND vias close to the caps are few. How is the GND connection under the IC?
Thanks
