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# LT1641 what is the link between current mode and output voltage!?!?!?!

LT1641 datasheet page 7 says:

"Once the voltage at the output has reached its final value,as sensed by resistors R3 and R4, the PWRGD pin goes high"

Okay output voltage has reached a level, but then what is the link between current limiting and output voltage?

Example 1:  Input is 24V, I set the timer to 500mS which the chip stays in current mode. Now the question is, how do I know if the chip is still in the current limiting mode if the output voltage has reached already the value set by resistors? This would easily lead to a situation when Powergood signal enables already the next stage, say a power regulator, when LT1641 still limits the current.

Example 2; I set the timer shorter than it is needed to fully load the capacitors on the output(next stage) so the last bit of voltage will just "jump" to the max, this would cause a surge current.

What the POWERGD signal should do to be useful, is to inform when the current mode has ended. FB pin should be used only to detect short circuit on output.

When you have no clue in which stage the current limiting is at the time, feels pointless to use PWRGD to anything.

Parents
• Feeding the PWRGD signal into a delay circuit with a duration of up to your chosen TIMER pin delay time would guarantee the LT1641 will be out of current limit before your next stage attempts to turn on.

Your question: "how do I know if the chip is still in the current limiting mode if the output voltage has reached already the value set by resistors?"

My answer: You can tell if the chip is in current limit by observing the current level with a scope. Or, you can look at the Hot Swap FET's gate-to-source voltage on a scope. If the voltage is above about 5V, this indicates that the FET is no longer being driven to limit current. The last indication that the IC is no longer driving the FET in current limit is that the drain-to-source voltage is close to it's Rds(on)*load current.

Thanks,

Ryan

• Feeding the PWRGD signal into a delay circuit with a duration of up to your chosen TIMER pin delay time would guarantee the LT1641 will be out of current limit before your next stage attempts to turn on.

Your question: "how do I know if the chip is still in the current limiting mode if the output voltage has reached already the value set by resistors?"

My answer: You can tell if the chip is in current limit by observing the current level with a scope. Or, you can look at the Hot Swap FET's gate-to-source voltage on a scope. If the voltage is above about 5V, this indicates that the FET is no longer being driven to limit current. The last indication that the IC is no longer driving the FET in current limit is that the drain-to-source voltage is close to it's Rds(on)*load current.

Thanks,

Ryan

Children
• So the PWRGD signal should be delayed to be longer than the current regulation mode to ensure the current mode has passed. Something like this:

The other thing is the ON pin, If I pull it LOW at any time, will the timer sequence start from the beginning?, This is for me alarming, that if ON pin is put LOW and the timer sequence is not reset, the surge on input will appear as soon as ON pin is pulled HIGH again.

"If the ON pin falls below its threshold voltage (1.233V),the GATE pin is pulled low and is held low until ON is high again."

Its not clear what is the use of Timer pin ? Which event will start discharging the TIMER capacitor so pin doesn't reach the crucial 1.233V and disable GATE pin?

"TIMER (Pin 5): Timing Input. An external timing capacitor at this pin programs the maximum time the part is allowed to remain in current limit."

Isn't the GATE capacitor to determine the slope aka GATE ramp? Why do we need additional TIMER pin for this?

• Yes, something like your drawing.

If the ON pin is pulled low, the GATE pin is also pulled low. When the ON pin is allowed to go high again, the GATE pin must also rise again before the FET can be turned back on. This is discussed on Page 7. The (restart) time it takes for this to happen is ≈CL*Vin/Iinrush. So, the FET Q1 is not on immediately after the ON pin goes high. If the TIMER pin's capacitor had charge on it before the ON pin went low, it will be discharged with 3uA as discussed on Page 8 and shown on the Block Diagram on Page 6. So, sizing C1, hence Iinrush, to get a restart time that allows for a full discharge of the TIMER pin capacitor is one way to affect the behavior it seems you desire - a reset of the TIMER before a restart.

The reason to use the TIMER pin is to set a delay before the FET turns off while it is in current limit. This allows the FET to limit current for a programmable time before the FET is turned off in order to protect it from blow ups.

As mentioned above, the TIMER always has a 3uA discharge (pull-down) current. As long as the IC is not actively current limiting with its resultant 80uA pull-up (charge) current on the TIMER pin, the 3uA will discharge the TIMER pin capacitor.

The GATE pin capacitor, C1, of Figure 5 determines the turn-on slew rate of the output.  Said another way, the charging current (Iinrush) of the load capacitor, CL. The TIMER pin simply determines how long the FET can stay in the current limit mode before it gets turned off by the IC.

Thanks,

Ryan

• Thanks for the explanation. What I try to achieve is a fast return to start position, which in normal configuration might not work since discharge rate is "slow". The requirement is to immediately discharge all timing functions as soon as supply is disconnected. So in case of re-connecting supply timing is restarted; slew rate and Timer.

Because Timing capacitor discharge rate is so slow, I need to boost it with the external elements for Timer and slew rate, the circuit which detects the supply interruption is done elsewhere.