LDO noise performance when cascaded from a buck in ADP5022

I want to cascade one LDO from one of the buck in the ADP5022, will the switching noise of the buck affect the LDO performance?

  • 0
    •  Analog Employees 
    on Apr 28, 2011 3:36 AM

    It depends, if the voltage difference between the LDO input/output is at least 300mV the PSRR of the LDO will well suppress noise below 100-kHz, this can be generated by transients on the buck output or the buck operating in PSM. If the voltage difference is small or the LDO operates in dropout the PSRR will deteriorate to a point where the noise at the input goes to the output. Switching noise generated by the buck, when operating in PWM, will not be suppressed by the LDO control loop because of the limited amplifier bandwidth however the output capacitor together with the board parasitic can help to suppress the switching noise, please refer to the PSRR curves provided in the ADP5022 datasheet  to estimate the suppression level around 3-MHz. In those cases it is required a high level of noise suppression it is recommended to add a LCR filter at the output of the LDO as shown in the attached figure, the resistor is needed to damp the resonance of the filter. Filter characteristic depends on the critical frequencies where the load circuit is particularly sensitive. 

  • Hi Maurizio,

    Can you give the design details of this Filter?Especially filter components calaculation and relation with ripple.

    or a simple example ?

    I want to use this as power supply for 16 bit ADC and a medium gain INAMP ? Usually I will not use a DC to DC to supply the ADC,Vref and INAMP.I will use a seperate LDO.

    but do you think with your filter I can save on the seperate LDO and still I can get the same performance?

  • 0
    •  Analog Employees 
    on Jul 6, 2011 9:04 PM

    Hi Chaitanya,

    As requested I have attached a document showing the proposed filter implementation and design, please note that this filter was designed to be effective above 100kHz with minimal resonance and targeting space constrained applications (main target for the ADP5022). The document assumes that the intrinsic high PSRR of the LDO is able to suppress supply ripple at lower frequencies. You may need to fine tune the filter performance according to your needs, the document here attached contains the guidelines for the filter design but let me know if you need additional information

    I understand from your reply that you would like to supply the ADC, Vref and INAMP directly from a switcher with a post filter, please note that the configuration suggested in this post is a switcher supplying the input of the LDO (Which is often the case for the ADP5022) and a filter placed after the LDO to suppress frequency above the MHz range where the LDO's PSSR is not much effective (This is common to LDO architectures due to the limited loop gain at higher frequencies).

    It is indeed possible to power noise sensitive circuits with a switcher and I have added few links to ADI documents showing some examples and considerations. In order to provide a more precise answer I will need to know more about your application, in the meantime I would like to offer some simple guidelines:

    • If the load current of the system you are trying to supply is low (say less than 50mA) it may be not convenient to use a switcher, first because the switcher efficiency in constant PWM drops quickly and may not be better than a LDO (of course additional information is needed to determine this). It is not recommended to enable a pulse skipping (PSM) or other low power modes when supplying noise sensitive circuits  this is because the switcher operates in bursts with variable frequency that will be difficult to tame with a simple filter.


    • Adding a RLC filter as suggested in this post for a high current loads could be problematic because the inductor series resistance (DCR) will insert a voltage drop therefore you may be forced to use a very big inductors to minimize the DCR. In addition the load may exhibit a transient current behavior which may make things worse, in this case the filter need to be modified to consider case like these. The links below show exactly this type of situation and solutions proposed.


    • Beside electrical noise it is also important to consider magnetic coupling from the switcher inductor to the nearby components, we have seen cases where a filter was not effective because of this, the solution was to find a type of inductor with better shielding performance, please note that even if an inductor is specified as "shielded" it may still have residual flux that is enough to perturb external circuit. Our experience shows that multilayer inductors are better than wire-wound in term of shielding because of the specific construction however you need to be sure that the multilayer inductor used can safely operate up to the max load current (Inductance in multilayer inductors drop quickly as the current increases especially for inductor values above 2.2uH).


    • It is important to consider the location of the power management section in relation to the noise sensitive load. If the load is far away, the supply trace may get polluted along the way therefore, in this situations it is better to have an LDO or the filter circuit very close to the load.

    Best regards,





  • Thanks for such a detail reply.

    Pls allow me to study this, I will come back in one or two days.

    Thanks once again !

  • Hi Maurizio,

    I have simulated and tested the filter circuit and yes it works better.

    The resistance helps to damp the over shoot in the transition region of the filter, I wonder can't we use a moderate ESR electrolyte that may serve both the purposes Capacitor and a  resistor and cost saving.This is about the post LDO filter which you have mentioned.

    I think for high speed ADCs the precision is low and even the ENOB is not high and hence it is quite ok to use the DC to DC directly.

    My application is Low frequency close to DC signal level coming from Accelerometer, I need pretty good precision Model 1 min 14 bit and Model 2 min is 21 bits.So I am designing with LDO inserted in between the DC to DC.I think for low frequency design with high precision we can not use the DC to DC directly, what do you think?

    I know that LDO rejects the Ripple and has a RRR and we are making use of that to stop the low frequency noise coming from DC to DC that can act as a noise floor to ADC and reduce the SNR.

    Few doubts about this,now a days all DC to DC are being operated in the MHz range to optimize for the Inductor Size and efficiency, do they generate so much nosie in the Low frequency region?Can't we place such filters at the output of the DC to DC to make it low noise only in high frequency region easily?Or it might add ESR and reduce the regulation?this is just a thought !

    What happens when there is overshoot in the Frequency response of a filter? does the noise in that region gets oscillated,resonated and amplified?

    Basically how the LDO removes the noise,ultimately it is just a Linear Transistor and an error amplifier configuration?

    And how the ADP2114 removes the strong noise contributed by the Buck architecture? usually on scope we used to see Noise in mV for other old DC to DC,some even gives noise if you place the probe physically over the inductor in the Air !!! Is there any special considerations done in the chip for Inductor cureent Ramp up?

    Pls give your excellent expert opinions

    Best Regards,