LTC7871: recommended layout for FET signal and sense resistor lines

Hello,

The stackup shown above is OK for 6 layers.

The SNS, SNSD and SNSA pins as well as the VFB, ITH, SETCUR, IMON, SS, FREQ, OVLOW/HIGH and UVHIGH are sensitive pins. The traces connected to the sensitive pins should be routed away from the high dV/dT traces which include the TG, BG, SW and BOOST traces in the switching stage and the PWM, CLKOUT, SYNC, SCLK, SDI, SDO and CSB signals on the analog side. For the LTC7871, the TG, BG, SW and BOOST traces will only be present around the gate drivers and MOSFETs. Therefore, for the circuit around the LTC7871, you will mostly need to keep the sensitive traces away from the other high dV/dT signals mentioned. These will have slower rise and fall times.

In the layout, avoid routing the sensitive traces in parallel with the high dV/dT signals. If they are routed in parallel, route 50mil or more of GND between them. In the pinout the high dV/dT pins are between pins 29 and 52. Plan the layout such that these traces do not intersect with the sensitive traces. Use the demo board as a guide. 8 layers is better, but 6 layers should be possible.

For the current sense traces, keep R1 (see diagram below) next to the switch node. Place the other components (R2, C1, R3 & C2) next to the LTC7871. R1 should not be next to the LTC7871 since one side of it is connected to the SW which is noisy. Same applies if the DCR sensing setup is used.

Best regards,

Mike

Thanks Mike.

• With the stackup mentioned earlier, Should the Layer 2 and Layer 5 be connected to each other with a lot of vias, and then connected in a star configuration along with Power GND ? Something like 
  
• In other words, is the GND plane in layer 2 and layer 5 is essentially meant to provide an isopotential field for layer 3 and 4. This would require low impedence/resistance between 2 and 5, correct ? 
• If the controller lines are routed on layer 4, it is almost impossible to avoid them crossing the rsense lines on the layer 3. Do you have any suggestion for this configuration?

Any updates on this question ? 

Hello,

Layers 2 and 5 are actually the power GND planes mentioned in AN136 and are common to the system. Therefore, the star configuration you drew is not required. These are the purposes of the GND plane:

• The GND planes shield the small signal traces from the high dv/dt and high di/dt components and traces on the top and bottom layers.
• The GND planes provide a  low impedance GND connections between circuits and components.
• The GND planes provide heat spreading.

Given the above, a low impedance connection between the GND planes is required. These are provided by the vias. On the demo board the vias connecting the GND layers are placed at the source of the bottom MOSFET and the return of the ceramic input capacitors. GND vias are also placed at the return of the ceramic output capacitors and elsewhere. Aim for 1A or more per 10 mil via if possible for the vias near the source of the bottom FET and ceramic input capacitors. 

Crossing of the noisy and sensitive traces is difficult to avoid completely for a 6 layer stackup. To minimize the cross-overs, follow the layout of the demo board. See below.

Note, the LTC7871 is on the bottom layer and the power section is on the top. The noisy side of the LTC7871 (pins 29-52) face the power section. When viewing the diagram, the PWM and SPI signals exit from the top and the current sense pins approach from the sides. The PWM signals will go directly to the LTC7060 gate drivers at the top of the diagram while the sense resistors are on the sides. Therefore, the two sets of traces should not come close. Depending on the location of the SPI controller, the SPI traces could interfere with the current sense traces. This may be inevitable. If they cross-over the SPI or PWM traces just once, then this is OK. However, they should not ever be routed in parallel.

To answer a previous question, the SPI controller and signals can be referenced to the GND planes mentioned above.

Best regards,

Mike

Hello,

Layers 2 and 5 are actually the power GND planes mentioned in AN136 and are common to the system. Therefore, the star configuration you drew is not required. These are the purposes of the GND plane:

• The GND planes shield the small signal traces from the high dv/dt and high di/dt components and traces on the top and bottom layers.
• The GND planes provide a  low impedance GND connections between circuits and components.
• The GND planes provide heat spreading.

Given the above, a low impedance connection between the GND planes is required. These are provided by the vias. On the demo board the vias connecting the GND layers are placed at the source of the bottom MOSFET and the return of the ceramic input capacitors. GND vias are also placed at the return of the ceramic output capacitors and elsewhere. Aim for 1A or more per 10 mil via if possible for the vias near the source of the bottom FET and ceramic input capacitors. 

Crossing of the noisy and sensitive traces is difficult to avoid completely for a 6 layer stackup. To minimize the cross-overs, follow the layout of the demo board. See below.

Note, the LTC7871 is on the bottom layer and the power section is on the top. The noisy side of the LTC7871 (pins 29-52) face the power section. When viewing the diagram, the PWM and SPI signals exit from the top and the current sense pins approach from the sides. The PWM signals will go directly to the LTC7060 gate drivers at the top of the diagram while the sense resistors are on the sides. Therefore, the two sets of traces should not come close. Depending on the location of the SPI controller, the SPI traces could interfere with the current sense traces. This may be inevitable. If they cross-over the SPI or PWM traces just once, then this is OK. However, they should not ever be routed in parallel.

To answer a previous question, the SPI controller and signals can be referenced to the GND planes mentioned above.

Best regards,

Mike

Thanks for the detailed info!