We are designing a 6 layer board (2oz outer and 0.5oz inner) with LTC7871. The DC2886 is an evaluation board, but has an 8 layers.
https://www.analog.com/media/en/technical-documentation/application-notes/an136f.pdf app recommend the follow layer configuration:
We aren't able to use Layer 1 or 6 for the FET gate line(output of PWM driver) and intend to use the layer 3 for sense resistor lines and layer 4 for the FET gate line(output of PWM driver). Since Layer 3 and 4 and within 8-10 mil separation, there could be cross talk between digital PWM line and the sense resistor line even though the layout will be done reducing the amount of overlap.
- Does the SNS, SNSD and SNSA amplifier remove noise that may be injected from the PWM driver ?
- Is there an alternate layout suggested for the system ?