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Use LTC4412 in My DC UPS

My DC UPS prototype

Hi!

I need help building a DC UPS. Did I understand correctly the idea of using LTC 4412 to control fully isolated MOSFET switchs? I am suggesting to use an external switching power supply (Wall Adapter) and a backup 12V gel or LiFePo4 battery. For periodic recharging of the battery, I plan to use a separate charging module, which will connect if there is power from the Wall Adapter and if the battery voltage is below 11 volts. The charge module will be connected to the battery with a VT5 transistor. The entire circuit will be controlled by a separate microcontroller.

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  • Hi, Ashapiro!

    Thank you for your help!
    I completely lost sight of the fact that DA1 requires power, and this power, in my case, must be taken from the battery!
    I have corrected my circuit according to your comments.

    Corrected Schematic

    I also wanted to ask you - Is it permissible to turn on transistors like this, as shown in the following diagram? This refers to the inclusion of a pair of transistors (VT1-VT2, VT3-VT4, VT5-VT6) drain-drain, and not source-source (A similar scheme for switching on transistors is often found in laptop power management circuits). In the case of a single transistor, the current must flow strictly from the drain to the source (in the direction of the built-in diode).

    Drain to Drain transistors pair

  • Hi Alex,
    There is another issue:

    The battery (primary supply) should be on the upper FET pair, connected to the GATE pin.

    I simulated your circuit below:

    The scenario above is if Battery=12V and Wall=0V. Notice that OUT=0V and IRLOAD=0A, even though battery is present.

    If you swap the supplies, so battery is on the “PRIMARY” FET pair, and wall is on the “AUX” FET pair, you get the following:

    Now, OUT=12V and IRLOAD=500mA when Battery=12V and Wall=0V. I believe this is the behavior you want.

    About back-to-back FET configuration:

    A common source connection is used to accommodate the FET’s VGS rating. If using common drain, the source would be on the supply side, so a high enough supply voltage could exceed the FET’s max VGS.

     

    Hope this helps,
    -Aaron

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  • Hi Alex,
    There is another issue:

    The battery (primary supply) should be on the upper FET pair, connected to the GATE pin.

    I simulated your circuit below:

    The scenario above is if Battery=12V and Wall=0V. Notice that OUT=0V and IRLOAD=0A, even though battery is present.

    If you swap the supplies, so battery is on the “PRIMARY” FET pair, and wall is on the “AUX” FET pair, you get the following:

    Now, OUT=12V and IRLOAD=500mA when Battery=12V and Wall=0V. I believe this is the behavior you want.

    About back-to-back FET configuration:

    A common source connection is used to accommodate the FET’s VGS rating. If using common drain, the source would be on the supply side, so a high enough supply voltage could exceed the FET’s max VGS.

     

    Hope this helps,
    -Aaron

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