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LTC3636 RUN PIN Impedance

1) Is RUN pins leakage current really that high (+/-4uA from datasheet)? I need a finer characterization, at least within working temperature range... am simulating a solution where there's a max 0.3 ohm PPTC between tank caps and feedback divider. It should shut the branch wether powergood gets deasserted longer than 30 mS, typically when the PPTC trips but also in case Vin should drop too low: it seems working, but i welcome suggestions. This is it:


2) This LM3636 comes in two versions, targeted to different Vout ranges. In my board i need a couple, one with ~ 1Vouts, and this one with 5.1V outs. Basing on datasheet, here LTC3636-1 version should be selected but i'd definitely prefer using two identical chips. So am planning to use the LTC3636 at 5.1Vout. 

Provided simulation design for LTspice seem is for the LTC3636 only, and it's behaviour shows decent just once increased the speedup cap on output feedback divider to about 220pF. Load step of 1.5A in 1 uS starting from 200mA produce a small, acceptable voltage glitch on outputs and no PGOOD drop...... .  Vith voltage is clean, stays most of time within range and clips at rails only for a brief time after load steps down.

One strange thing i noticed is the presence of irregularities on Vith (confirmed by corresponding double or triple pulses at sw node) during the stable part of soft start ramp. Apart the very beginning where some irregularities are expected, the s.s. ramp is generally very clean; and zooming in, the sw-node sqw pulses are singles and evenly spaced (1 uS in my 1 Mhz fsw design).

But from time to time disruptions occurr and denser bursts of 2,3 or 4 pulses, seemingly regular in width, occurr at the output. Vith shows variations at those points.

Is this any known artifact with simulation? or what should i look at, to fix?

Finally:  ==>> Could i trust ltspice, and go ahead with these passives sizes? 

Otherwise, how could i simulate the LTC3636-1 part in Ltspice, for seeing myself the difference?