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LT1764A Recommended for New Designs
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Paralleling LT1764a

		
	
				

			

									
					    yygomez
					
							

            
            			
				
									
											
			
			
				
			
			
			    	
			                    
                
				                on Jul 1, 2021 
				
			
			
		

		
		                    	    

        	    
Thread Summary

                The user is experiencing oscillation issues when paralleling two LT1764A linear regulators. The final answer suggests that the oscillation might be due to difficulties in establishing a proper master-slave configuration and recommends reviewing the simulation and sharing the exact input and output specifications, as well as the schematic and layout. Adding a 10pF cap to simulate PCB trace length in LTSpice caused oscillation, which was mitigated by adding a 0.1uF cap from the op amp +in to ground.
                        	    

                
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Hi,


I am working on an application that required paralleling two LT1764A in order to get the current we needed.


We basically implemented the circuit exactly as recommended on the LT1764 datasheet (page 20) : https://www.analog.com/media/en/technical-documentation/data-sheets/1764fb.pdf


 


The problem we have is the circuit is oscillating badly, investigating I found the article: https://www.analog.com/en/technical-articles/paralleling-linear-regulators-made-easy.html.


I was trying to reach Kevin, kevin.scott@analog.com the author of the article but looks like the listed email is dead.


I wonder if you can give me some advice. 


I have the  LTSpice simulation file. Note the pcb trace from the Op amp output to the Resistor is a little long, adding 10pF to simulate that makes the circuit oscillate similar to what we are seeing in our application.


The only way I found to stop the oscillation is adding a 0.1uF cap from the Op Amp +in to ground.


Thanks in advance and best regards,


Jorge Gomez.

			

			
									
		                             
                        

    

                                            
                 parallelling
                
                                                    
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                 parallel operation
                
                                                    
                 LDO Linear Regulators
                
                                        
                                            
                
                
                                        
                                            
                
                
                                
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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Jul 29, 2021 4:13 AM
            
            
						
			            		
    
		
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    Hi Jorge,
    

    Can you tell us what is exact input and output specs of your application?
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
				
				
				
				
		
		
    
			
		
    
	
    

    

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    •  Analog Employees  
    
            
						
                            
            
            				
            
                on Aug 10, 2021 8:19 PM
            
            
												
						in reply to Fil
					
										
			            		
    
		
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    Hi Jorge,
    

    Hope you are doing well.
    

    One possible reason for oscillation is that your circuit is having a hard time establishing a proper master-slave configuration. In my LTspice simulation, (the simulation was in reference to that of the schematic you have shown here) adding a 10PF on the output of the op amp didn't result to oscillation. Can you share your simulation here?  Also as what Fil said before, can you tell us the exact input and output specifications and if possible, a schematic and layout of your design?
    

    Regards,
    

    Siglo
    
			
    

		
			
	      

		
		
	
    
	
    
		
    
			
		
    
	
    
	
    
		
						
						
						
				
				
				
		
		
    
			
		
    
	
    

    

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