LTC4365
Recommended for New Designs
The LTC4365 protects applications where power supply input voltages may be too high, too low or even negative. It does this by controlling the gate voltages...
Datasheet
LTC4365 on Analog.com
Our design uses LTC4365. Input voltage is 30V and expected operating current is 1.5A. A total of 240uF capacitance is present in the output of the protection circuitry (LTC4365). We have observed that after 1st power cycle the input side N Channel MOSFET has shorted (D-S Short). the LTC4365 is responding to the UV/OV faults hence we conclude that the LTC4365 device is fine and not damaged.
We are using Lab power supply for the tests.
Pl note that the failure is reproducible and all the boards (5+) failed after the 1st power cycling.
Analysis in a similar implementation in the design:
We have performed inrush current measurements and the inrush current is around 8A.
We have probed the Vin, Vout, Gate & Shutdown pins and the following are the observations (refer the diagram below):
In the above, we have increased the Cgate from 2.2nF to 5.6nF and following is observed (refer the diagram below):
Pl let us know:
Hi,
We have added 5.6K Rgate resistor as recommended in the LTC4365 datasheet (Fig 14 in the datasheet, given below) with Cgate of 5.6nF. This has reduced the oscillations at the GATE & Vin but there is a huge dip in the input voltage for a brief period. We attribute this to the huge inrush current at start-up.
Pl find the waveform attached, FR.
Looks like the inrush current protection feature of LTC4365 is not working during this period.
Though the circuit is designed for <1.5A of inrush current we are seeing an inrush current of around 8A when the power is turned-ON.
Pl let us know what changes needed in the circuit to make it work with inrush current protection as needed. Also let us know if there are other factors that could have caused the MOSFET failure.
Hi Pons,
The schematic you posted does not have the 240uF of output capacitance that you said.
Also, it is not clear what your load is that draws 1.5A. Disconnect it for now while we troubleshoot the LTC4365.
As I understand it, you turn on the supply on the VIN side, and the load draws 8A of inrush, and the high VDS and ID kills the FET. This is an SOA failure.
On your scope-shots, I do not see a current waveform. How do you know you are drawing 8A?
Useful waveforms to monitor would be: Inrush current, VOUT, GATE.
Let’s examine the stress on the FET during start-up:
Using CGATE=2.2nF, your spread of possible inrush currents is: 1.2A (min), 2.2A (typ), 3.6A (max).
It takes 2ms to charge 240uF to 30V with 3.6A.
According to the FET’s SOA graph below, the FET can handle 30V,4A for between 100us to 1ms.
The FET cannot handle the start-up stress, and will likely fail.
We can iterate with a higher CGATE to lower the inrush. Aim for 1ms, the longest time on the FET’s SOA graph.
Increase CGATE to 10nF, the spread of inrush currents is now: 262mA (min), 480mA (typ), 800mA (max).
It takes 9ms to charge 240uF to 30V with 800mA.
The FET can handle 30V,800mA for only 1ms.
The FET cannot handle the stress needed to charge the output cap in 1ms, the longest curve on the FET’s SOA graph.
You need to choose a FET with higher SOA. Looks for FETs with 10ms curves.
To remove the oscillations at start-up, add 10Ω resistors as close as you can to the gate pins of the FETs. This will buffer the trace inductance from the FET’s capacitance.
Summary:
-Aaron
Hi Aaron,
Thanks for the detailed response.
We have measured inrush current using a series resistor.
A total of 200uF input capacitors are used in the design and including the output cap (47uF) of the protection circuit it is 240uF. In the circuit we are also considering to reduce the total capacitance in the output of the protection circuit.
Note: Waveforms shared are from the similar circuit in our design with less capacitive loads (Total of 140uF including 47uF at the output of the LTC4365) and lesser number of DCDCs. We would like to analyze the issue in the working circuit and after making improvements we will be moving to implement the fixes in the circuit which has MOSFET failures.
We have made some tests Today and below are the observations. We are also checking in parallel if there is a better MOSFET in the same footprint.
In the current design we are unable to add 10Ohms resistors for the Gate due to the space constraints.
We have multiple DCDC converters connected to the output of the protection circuit.
We have disabled the DCDCs (loads of the LTC4365 circuit) but the observation is same as the one with DCDCs enabled by default. Hence we conclude that the capacitors at the output of the LTC4365 is playing the major role and not the DCDCs.
Fig: Waveforms with all 3 DCDCs enabled with a total cap of 140uF (Vin (Pink), Vout (Blue), SHTDWN) Cgate/Rgate: 5.6nF/5.6K
We have disconnected all the loads at the output of the LTC4365 except the 47uF output capacitor and the waveform is smooth. This is with Cgate/Rgate of 5.6nF/5.6K. Momentary spike at the input voltage (dip) not observed
Fig: Waveforms with all 3 DCDCs disconnected (Only 47uF present at the output of the LTC4365) Cgate/Rgate: 5.6nF/5.6K
Even if we connect one load (DCDC) with 30uF capacitance + one DCDC, we observe the momentary dip in the input voltage. Total capacitance is 47uF+30uF = 77uF.
Fig: Waveforms with only one DCDC is connected & other 2 disconnected (Total of 77uF present at the output of the LTC4365) Cgate/Rgate: 5.6nF/5.6K
When the Cgate is increased to 10nF and Rgate removed, the input voltage dip has decreased but we observe multiple momentary dips.
Fig: Waveforms with only one DCDC is connected (Total of 77uF present at the output of the LTC4365) Cgate:10nF & Rgate-Not used
Pl let us know the following:
a. What is the max value of Cgate we can use?
b. What is the impact of the increased Cgate value on the performance of the LTC4365 circuit? Our hardware will be used in controlled lab environment and powered by bench power supplies.
c. We see better performance without Rgate resistor. What is the impact of not using Rgate in the design.
