ADSP-2148x E-pad question

Hello

I have just finished reading the EE- 352 Engineering note regarding E-pad packages and mounting techniques. One thing I am not clear of is you don't say whether or not you use thermal relief's or direct connects on the ground plane connecting via's. Obviously direct connection would give you better electrical connection and lower thermal resistance to the ground plane but would it alter the temperature profile needed for reflow ? ie which would be better from the point of view of manufacturability ?

regards

david

Parents
  • Thanks Al

    How big is the center hole that you use ?

    I have made provision for a 5 mm hole in the middle of the pad so I can solder it. I also did what they have suggested in EE-352 and used an outer perimeter of small vias and tent them using solder mask.

    Do you think the large hole could be left in the production units even if most of the paste drops into the hole ? I don't mind having to rework the board after they go though production. According to EE-352 you need to experiment with the temp profile and amount of paste until you minimize the number of solder voids under the pad. Sounds like a hit and miss process to get it right and unless you have an xray machine how would you know ? I like the idea of the large pad hole do I can make sure it is done right which is why I asked about thermal reliefs because I know that soldering to a pad directly connected to a plane can be a bit tricky as the plane soaks up all of the heat from the iron.  However that could work in favour in order to minimize heat stress on the chip.

    Also the switcher IC I am using ADP2323 recommends that I bake the chip at 120 degrees C for 24 hours before reflow. Is this really neccessary if I hand solder the chip onto the board ?

    regards

    david

Reply
  • Thanks Al

    How big is the center hole that you use ?

    I have made provision for a 5 mm hole in the middle of the pad so I can solder it. I also did what they have suggested in EE-352 and used an outer perimeter of small vias and tent them using solder mask.

    Do you think the large hole could be left in the production units even if most of the paste drops into the hole ? I don't mind having to rework the board after they go though production. According to EE-352 you need to experiment with the temp profile and amount of paste until you minimize the number of solder voids under the pad. Sounds like a hit and miss process to get it right and unless you have an xray machine how would you know ? I like the idea of the large pad hole do I can make sure it is done right which is why I asked about thermal reliefs because I know that soldering to a pad directly connected to a plane can be a bit tricky as the plane soaks up all of the heat from the iron.  However that could work in favour in order to minimize heat stress on the chip.

    Also the switcher IC I am using ADP2323 recommends that I bake the chip at 120 degrees C for 24 hours before reflow. Is this really neccessary if I hand solder the chip onto the board ?

    regards

    david

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