LTC4151 problems with internal address pointer(when BYTE R/W)

Hi everybody!

Please help in my case

Ive triying to establish valid data reading from LTC4151

At first I decided to R/W in TEST MODE

So I do the following!

- 1 Set 7 bit address, 80 kHz bit rate
- Store to control register 0x10 to set up TEST UP
- Store to MSB of SENSE register 0x55
- Store to LSB of SENSE resgister 0xAA
- Read MSB of SENSE register - and IC get 0x55
- Read LSB of SENSE reister - and IC get 0x55 instead of 0xAA

The same situation at the reast pair of register (in TEST MODE)

And then I read control register before READ MSB and LSB of SENSE register it also gets 0x55 instead of 0x10

Please help, I didin understand
I chek all by oscilosope and what it gets:


a6a5a4a3a2a1a0R/nWACKb7b6b5b4b3b2b1b0ACKb7b6b5b4b3b2b1b0ACK
1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0


a6a5a4a3a2a1a0R/nWACKb7b6b5b4b3b2b1b0ACKb7b6b5b4b3b2b1b0ACK
1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0

a6a5a4a3a2a1a0R/nWACKb7b6b5b4b3b2b1b0ACKb7b6b5b4b3b2b1b0ACK
1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0


a6a5a4a3a2a1a0R/nWACKb7b6b5b4b3b2b1b0ACKb7b6b5b4b3b2b1b0ACK
1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0


a6a5a4a3a2a1a0R/nWACKb7b6b5b4b3b2b1b0ACK//S//a6a5a4a3a2a1a0r/nWACKb7b6b5b4b3b2b1b0nACK
1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 0 1 0 1 0 1 0 1 1

a6a5a4a3a2a1a0R/nWACKb7b6b5b4b3b2b1b0ACK//S//a6a5a4a3a2a1a0r/nWACKb7b6b5b4b3b2b1b0nACK
1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 1 1 1 1 0 0 1 0 1 0 1 0 1 1

  • 0
    •  Analog Employees 
    on Jun 16, 2021 1:19 PM

    Moved to the forum where someone can better help answer your questions.

  • +1
    •  Analog Employees 
    on Jun 17, 2021 9:34 PM

    Greetings Addigde,

      This is an interesting problem, and I think we will need some more information to find out what is going on.  Bits 2:0 of register B (0x01) are not writeable and should always return 0 when read back.  Bit 3 of the same register is the ADC busy bit and should also return 0.  I deciphered all of your scope bits and nothing looks like its out of protocol.   Here are my questions:

    What are you using as a master? 

    Did you develop custom code for I2C communication?  If so can you send the code?

    Can you provide a schematic?

    Are you using LTpowerPlay?

    Can you try performing a write/read WORD on register A(0x00) and let me know the results?

    If you are uncomfortable posting any of the requested information in here, please feel free to email me at brad.lovell@analog.com 

    Thank you and best regards,

    Brad

  • Dear Brad!

    Thanks a lot for your support!!

    I think I have found the reason but not suer

    I use STM32F429 as master and HAL library

    First I tried to do application layer using blocking functions HAL_I2C_transmit and HAL_I2C_receive

    But these fuctions cant do reastart adter write and before read

    So I deceided what when I do read with separated wirte before I always read 0x00 address

    Becuase of that I change API on 

    ( HAL_I2C_Master_Seq_Transmit_IT()
     HAL_I2C_Master_Seq_Receive_IT()

    And these API gives non blocking operation due to interrapts operation

    And here I met another problem, when I do read with restarted write I get the delay between write and read about 5 ms, can it bring any problem or be the problem?

    And Im not sure of data correction that read from

    I gues that It only one way to check correction is to write and read in test mode

    And maybe you can clarify what value I can get from first contrl reg reading?

    Please help!

    Thanks in advance

  • 0
    •  Analog Employees 
    on Jul 1, 2021 9:21 PM in reply to Addigde

    Greetings Addi,

       Can you post or email me a scope shot of one of these failed transactions?

    Thank you and best regards,

    Brad