ADP151 draws high current with output capacitor; outputs +0,2V without

Hi,

I designed three ADP151 LDOs (two 2,5V and one 1,8V) into my latest circuit.

Yesterday I got the PCBs and was suprised in a way.

All three are drawing too high currents without loads. If I would let them they would draw more than 100mA (I tried it).

After some experiments I removed the output capacitors. This had the effect, that the current was as specified at the datasheet.

(http://www.analog.com/static/imported-files/data_sheets/ADP151.pdf)

Initially there had been a 100nF input capacitor and a 1uF at the output. The former because the supplying circuit allready provides a 10uF cap.

But for the tests there is just a benchtop power supply (Keithley).

I tried different configurations with 1uF, 10uF capacitors at input and output. Applied and removed load (about 3mA, which is the intended load). At last I reduced the input voltage from 5V to 2,9V resp. 2,2V. But in vain. The output was 0,2V too high without output capacitor or the current was too high if it was connected.


Temperature is about 23°C.

When I had 1uF each on input and output I did a measure with the oscilloscope. I measured a sawtooth oscillation with a 3,8ms period, with about 400mV Peak2Peak and about aV Average (but the supply limited to 1,4V then due to the very problem). Even without an output capacitor there is a slight sawtooth wich parameters I acutally not remember.

I, most likely, did something wrong with the selection of the capacitors. But had reason, I assume.

The datasheet requested 1uF at input and output, with ESR below 1Ohm. On page 4 it request a maximum ESR of 0,2Ohm. But both without specifiying the measuring frequency. But ESR is usually specified at a certain frequency.

However, as I have only a small set of capacitors available, I tried only two.

1. 1uF Samsung X5R

CL10A105KA8NNNC_C3.pdf

where ESR is below 1Ohm above 90kHz

2. 10uF Murata X5R

http://psearch.murata.com/capacitor/product/GRM188R60G106ME47%23.html

with ESR below 1Ohm above about 800Hz

3. 1uF Murata X5R

http://psearch.murata.com/capacitor/product/GRM188R61C105KA93%23.html

with ESR below 1Ohm abouve 400kHz

I read some application notes (f.e. AN-1072), even some works about LDOs and their quirks but can't figure out what's wrong.

The layout deviates from the one suggested in the datasheet in the way, that the capacitors are not placed along the long side, but along the short side. I saw that when the layouter showed its work but I thought it was OK anyway, as they are located near the IC.

Any hint or suggestion would be appreciated very much.

  • 0
    •  Analog Employees 
    on Jan 17, 2013 11:38 PM over 8 years ago

    Mikey,

    I am surprised first of all that all 3 are having the same problem. If it was instability related then I would expect additional current drawing but not 100mA. This sounds more like there is something else on the output of the LDO drawing current. A short? a polarized cap inserted backwards?

    Looking at your layout, the placement is fine but I do not see a connection between the GND side of the input and output cap to GND pin/net. I see a via in the center of the ADP151 package and I see a via next to the input cap, but no via next to the output cap. The via next to the input cap is not connected to the GND of the cap on the same layer. So is it possible that both input and output caps are not grounded?

    Regarding the ESR rating of the caps, these capacitors are fine but make sure you account for the voltage derating of the capacitors at the voltage of interest, it can be as much as -40% for example for the 4V cap operated at 2V.

    Best Regards,

    LucaV

  • Luca,

    thank you for your kind answer.

    >I am surprised first of all that all 3 are having the same problem.

    I must confess, that I can definately say so for only two of them. I am sorry.

    But there are positively two, the one 2,5V and one 1,8V concerned.

    ( P.S.: As I saw right now, part of the title may be misunderstood:

    If the output capacitor is NOT connected the output voltage is by 0,2V higher than the nominmal value. 2,7V instead of 2,5V and 2V instead of 1,8V. Sorry for that.)

    >If it was instability related then I would expect additional current drawing but not 100mA.

    That's good to know. But they would definiately draw more than 100mA if I would let them. Only current limit of the power supply hinders them.

    >This sounds more like there is something else on the output of the LDO drawing current. A short? a polarized >cap inserted backwards?

    That's likely from your point of view, I must concede. But I can exclude that possibility by some probability, because I designed the circuit with some solder bridges right behind the outputs (and the capacitors) just for the purpose of implementation. The bridges are open now and their intended loads are positively not connected right now.

    Additionally I would expect the current to be high in either case then (if a shortcut or anything else would be located right at the output). I like to say: If the output capacitor is not connected I would expect a shortcut to draw some high current either. But it does not. If the output capacitor is removed the current is about 20uA as stated in the datasheet. Would you confirm that? Hovever, I think there is a slight probability that etching of the PCB left over a small piece of copper somewhere. I will check it tomorrow.

    >I do not see a connection between the GND side of the input and output cap to GND pin/net.

    OK. Could have made it more obvious or at least explain it. I switched of polygon fill.

    Now I filled the ground polygon with red (at home with paint) and appended it again. It's border is green (please note that the traces are green to, but they are surrounded by black or connect to blue).

    Both vias are connected to ground.

    Regarding the capacitance deration, I am not sure what to do about it.Considered that, I would conclude that even a 10uF, derated to about 6uF is too small. Do you mean that?

    As result I take:

    1. Possible (relatively) high resistance copper remainings.

    2. Current drawn, when output capacitor present, is unexpectedly high when considering oscillations.

    3. Capacitors effective value possibly still too low due to deration.

    4. ESR from you point of view sufficient for all three capacitors mentioned.

    When I read my (this very) answer again, I got the impression that it sounds like: "Yes, but..." and may induce the feeling that I am not willing to accept or even think about your answer. Please be sure that I took it serious and appreciate it.

    Please let me, despite that, ask again for the issue about the ESR specification from the datasheet, which, as I wrote, from my point of view, lacks the naming of the respecitve frequency. Could you say something about it, please?

    Regards,

    Mikey

  • It finally turns out that the Keithley Sourcemeter 2410 was the source (sic) of the problem. But I'm not sure if this is a problem of the individual or a constructive issue or a matter of calibration.

    When it is in source mode with measuring voltage and the current goes high while loading capacitors, it goes into limiting mode. Does not matter, even if the current limit is set to 200mA which shall enough for loading the caps.

    In limiting mode the voltage is regulated down to about 1,4V. In fact the Sourcemeter turns into a current source.

    If one then switch the measure mode to current, it shows the expected value and the LDO functions correct. Switching back to voltage measure show the nominal input voltage (5V in my case). If the current measure mode is selected on the Sourcemeter before turning on its output, everything is fine.

    Even a 1uF capacitor works.

    So, finally it was'nt an issue regarding capacitors nor the PCB.

    Thank you all, for reading and answering.

    Best regards

    Mikey

  • 0
    •  Analog Employees 
    on Jan 24, 2013 3:16 PM over 8 years ago

    Hi Mikey

    I've run into similar problems when using the 2400 series source meters to measure current consumption of camera chipsets.  There are two limits available on the Keithley - there is a current limit in current source mode and a separate compliance limit which limits the current in voltage source mode.  Conversely the compliance limit limits voltage during current source operation.  Setting the compliance higher should hopefully fix your measurement problem.  There is a hard limit depending on the voltage range you are using - see section 3-6 of the Keithley manual for details of the limits and how to adjust them. 

    Regards

    Tim

  • Thank you Tim, for your answer. I didn't realize immediately what the impact of that two different limits was and how to handle that. I only took your answer, chewing on it until I, after a week, got the clue. :-)