faster turn off of the passing fet of LT4356-1

Hi, all,

just to make it clearer, I am seeing the capacitor 47nF is discharging very slowly after the power is off. My input is 28V. The 47nf discharges quite fast from ~40V to 10V. But the 10V is maintained for quite some time, roughly few seconds or more, i guess. I am not able to measure it because as soon as I put a scope probe on the gate pin, then it is discharging very quickly. I am puzzled why this is happening. Anyone is kind enough to enlighten me?

Hi, all,

just to make it clearer, I am seeing the capacitor 47nF is discharging very slowly after the power is off. My input is 28V. The 47nf discharges quite fast from ~40V to 10V. But the 10V is maintained for quite some time, roughly few seconds or more, i guess. I am not able to measure it because as soon as I put a scope probe on the gate pin, then it is discharging very quickly. I am puzzled why this is happening. Anyone is kind enough to enlighten me?

Hi, AD experts, would you be able to advice? Thank you.

zach, could you please advice? Thanks. 

Hi Dyu,

How large is inrush that you want to minimize? Maybe you need to start with reviewing how much capacitance you have at output load, review inrush without inrush control then decide what R and C values you require. As you described, you may need to reduce value of 47nF or adjust R value.

Hi, Fil,

Thanks for coming back to this topic. Without the RC, the inrush current is around ~60A peak 100us. With the 47nF in place, I captured the inrush current plot against the output voltage after the pass FET as below. Channel 1 is output voltage and channel 4 is the inrush current with a conversion rate of 1V/A. Therefore it is reduced to around 1.6A peak 2ms at the first peak. 

At the output i have around 300uF of ceramic cap as shown below. 

I think this 1.6A peak is still acceptable by the customer. therefore i am planning to reduce the 47nF.

Any idea?

Dyu

Hi Dyu,

You have pretty big & capable FETs there.  It should not hurt if you reduct 47nF and allow more inrush current through the FETs. You have to make sure the inrush is able to be handled by FET SOA.

Hi, Fil,

The customer is worried that the high inrush will be tripping their power supply connected to other subsystems. If I am going to stick with 47nF in this case, what is the recommended the parallel drain resistor value?

Or is there any active draining circuitry to discharge the cap during the off period?

Dyu said:

therefore i am planning to reduce the 47nF.

Any idea?

sorry. typo. I am not planning to reduce instead.

Hi Dyu,

I don’t think we have any other suggestion except to reduce resistor value. The 47nF charge “drain” resistor during turn-off may be put across FET gate-to-source instead of gate-to-ground. Again, this is a case where you have to do several trials in bench in order to achieve optimized design. Good luck!

Hi, Fil,

Thanks. Can you enlighten me over the advantages of putting the resistor across gate-to-source instead of gate-to-ground? thank you. 

Dyu