ADM1177 TIMER pin behavior

Hi Moto

1) VTIMER

   a) When VTIMER reach to 0.2V then VGATE start to rise up, at (3) , I think.

     Is it correct?

ren- yes, after the initial timing cycle (which ensures the hardware connection and allow input to be stabilized) the gate will start to rise.

   b) After VTIMER reached to 0.2V, it will rise immediately, I think.

    What is the trigger of VTIMER rising?   (3)-(4)

ren- two things can trigger the timer to rise

one is initial timing cycle, triggered by VCC coming out from UVLO AND ON pin above threshold.

any toggling of ON pin after the initial timing cycle without power cycling the part will not cause initial power cycle to start.

the second event is the current regulation, this means if the differential voltage on the sense pins (current) reaches above circuit breaker limit (i think it is called overcurrent fault timing threshold on ADM1177) voltage. in this case the hotswap controller will try to regulate the current to the regulation voltage (overcurrent limit threhosld on ADM1177) and start the timer. If current ramps down, timer will be discharged slowly. If over current persists until timer reaches the high threshold, controller will turn off the GATE.

In the current regulation state, the external NMOS could have quite a bit power to dissipate, especially in the load short circuit event where you have current in regulation and large voltage drop across the FET.

the timer is a way to protect the FET from over heat/damage in such event.

I noticed you have made the bottom level of timer to be 0.2V, that is not correct. the timer will normally stay at 0V. 0.2V is just a threshold used to detect if it is low.

2) VGATE

   a) VGATE control ILIMIT current. so VGATE is flat at that time.   (3)-(4)

ren- no because your output voltage is still rising. to keep the same current your gate will also need to rise.

   b) VGATE will full "ON" ater (4)

      This circuit check voltage between VIN and VOUT, and that is trigger of external FET's full "ON", I think. 

      What is the trigger of Vtimer charge off / VGATE full ON?

ren- current decreases below the circuit breaker threshold (overcurrent fault timing threshold), in another word, the load capacitor is charged up and no longer demand extra current.

3) Current

   a) VGATE will down  if Irsense current is over IOCTRIM after (4).  is it correct?

ren- see comment above.

   b) VOCFAST active between (3) and (4) ?

ren -no, i believe this is not triggered in normal hotswap event shown in figures

The datasheet explains when this threshold is used.

If the fast overcurrent tripthreshold, VO C FA S T, is exceeded, the 1.5 mA to 7 mA GATE pull-down is turned on immediately. This pulls the GATE voltagedown quickly to enable the ADM1177 to limit the length of thecurrent spike thatpassesthroughanexternal FET and to bringthe current through the sense resistor back into linearregulationas quickly as possible. This process protects thebackplane supplyfrom sustained overcurrent conditions that may otherwisecausethe backplane supply to droop during the overcurrent event.

If you are interested, i have attached some simulation models for ADI hotswap controllers, they are spice based and the user guide is here.

They are good tool for understanding the behavior of the part.

we don't have one for ADM1177 but ADM1170-2 should be close enough.

ren

Hi Moto

1) VTIMER

   a) When VTIMER reach to 0.2V then VGATE start to rise up, at (3) , I think.

     Is it correct?

ren- yes, after the initial timing cycle (which ensures the hardware connection and allow input to be stabilized) the gate will start to rise.

   b) After VTIMER reached to 0.2V, it will rise immediately, I think.

    What is the trigger of VTIMER rising?   (3)-(4)

ren- two things can trigger the timer to rise

one is initial timing cycle, triggered by VCC coming out from UVLO AND ON pin above threshold.

any toggling of ON pin after the initial timing cycle without power cycling the part will not cause initial power cycle to start.

the second event is the current regulation, this means if the differential voltage on the sense pins (current) reaches above circuit breaker limit (i think it is called overcurrent fault timing threshold on ADM1177) voltage. in this case the hotswap controller will try to regulate the current to the regulation voltage (overcurrent limit threhosld on ADM1177) and start the timer. If current ramps down, timer will be discharged slowly. If over current persists until timer reaches the high threshold, controller will turn off the GATE.

In the current regulation state, the external NMOS could have quite a bit power to dissipate, especially in the load short circuit event where you have current in regulation and large voltage drop across the FET.

the timer is a way to protect the FET from over heat/damage in such event.

I noticed you have made the bottom level of timer to be 0.2V, that is not correct. the timer will normally stay at 0V. 0.2V is just a threshold used to detect if it is low.

2) VGATE

   a) VGATE control ILIMIT current. so VGATE is flat at that time.   (3)-(4)

ren- no because your output voltage is still rising. to keep the same current your gate will also need to rise.

   b) VGATE will full "ON" ater (4)

      This circuit check voltage between VIN and VOUT, and that is trigger of external FET's full "ON", I think. 

      What is the trigger of Vtimer charge off / VGATE full ON?

ren- current decreases below the circuit breaker threshold (overcurrent fault timing threshold), in another word, the load capacitor is charged up and no longer demand extra current.

3) Current

   a) VGATE will down  if Irsense current is over IOCTRIM after (4).  is it correct?

ren- see comment above.

   b) VOCFAST active between (3) and (4) ?

ren -no, i believe this is not triggered in normal hotswap event shown in figures

The datasheet explains when this threshold is used.

If the fast overcurrent tripthreshold, VO C FA S T, is exceeded, the 1.5 mA to 7 mA GATE pull-down is turned on immediately. This pulls the GATE voltagedown quickly to enable the ADM1177 to limit the length of thecurrent spike thatpassesthroughanexternal FET and to bringthe current through the sense resistor back into linearregulationas quickly as possible. This process protects thebackplane supplyfrom sustained overcurrent conditions that may otherwisecausethe backplane supply to droop during the overcurrent event.

If you are interested, i have attached some simulation models for ADI hotswap controllers, they are spice based and the user guide is here.

They are good tool for understanding the behavior of the part.

we don't have one for ADM1177 but ADM1170-2 should be close enough.

ren