LT3796 SCAP/EDLC charger

Hello

Could you recommend solution for EDLC charging based on LT3796, please?


Design requirements:

- Input voltage range 36-60VDC.
- Output: max. 55VDC, ~1F EDLC, charge current ~ 1-1.5 A


I think Buck-Boost/SEPIC should be used. But I can`t find any recommendations\calculations in LT3796 Datasheet for such operation (buck-boost/sepic supercapacitor charger).
There are only typical application on page 29. I redraw schematic to LTspice and perform some modelling. But it`s not clear how frequency folding circuit calculated.
Will be grateful for any recommendations, especially for LTspice files examples (if possible)

-- Best Regards

Top Replies

    •  Analog Employees 
    May 21, 2021 +1 suggested

    Hi Levandovsky,


    I think Buck-Boost/SEPIC should be used. But I can`t find any recommendations\calculations in LT3796 Datasheet for such operation (buck-boost/sepic supercapacitor charger…
Parents
  • 0
    •  Analog Employees 
    on May 21, 2021 8:37 AM

    Hi Levandovsky,


    I think Buck-Boost/SEPIC should be used. But I can`t find any recommendations\calculations in LT3796 Datasheet for such operation (buck-boost/sepic supercapacitor charger).

    SEPIC would be ideal for you especially if you want positive output. You can use page 29's typical application.

    . But it`s not clear how frequency folding circuit calculated.

    I'm not sure if you're referring to this, but in page 14, it discusses the relationship of Qg of your Nmos of your choice, and the Fosc/Fsw. INTVcc has voltage range between 7.4-8V. 

    Regards,

Reply
  • 0
    •  Analog Employees 
    on May 21, 2021 8:37 AM

    Hi Levandovsky,


    I think Buck-Boost/SEPIC should be used. But I can`t find any recommendations\calculations in LT3796 Datasheet for such operation (buck-boost/sepic supercapacitor charger).

    SEPIC would be ideal for you especially if you want positive output. You can use page 29's typical application.

    . But it`s not clear how frequency folding circuit calculated.

    I'm not sure if you're referring to this, but in page 14, it discusses the relationship of Qg of your Nmos of your choice, and the Fosc/Fsw. INTVcc has voltage range between 7.4-8V. 

    Regards,

Children
  • Hi Audison

    Thank you for answer.

    Frequency folding circuit build around Rt resistor (Q1, R3-R5, R10 C5), page 29.

    Also I would like to know how compensation was calculated for this circuit.

    Regards,

    Victor

  • 0
    •  Analog Employees 
    on Jun 16, 2021 6:02 AM in reply to Levandovsky

    Hi Levandovsky

    Apologies for late reply!

    Frequency folding circuit build around Rt resistor (Q1, R3-R5, R10 C5), page 29.

    The Rt pin has a very complex circuit that determines the switching frequency so we dont have all the necessary variables. Qualitatively, as the Vout increases, it drives more current from Vref to Q1. This drives the A13 from Functional Block diagram less current, which means it 'saw a larger resistance' that folds back the frequency. The actual frequency computation is within the block of oscillator that depends on the amount of current being pulled to Rt by A13.

    Also I would like to know how compensation was calculated for this circuit.

    You need an open-loop current-mode SEPIC for the big picture which I currently don't have. But Rc and Cc together is a Lag compensator, and you can follow the equation for you to have a clue:

    fpc = 1/(2pi(Rc+Ro)Cc)
    fzc = 1/(2pi(RcCc)

    where fpc < fzc. 

    Ro is the output impedance of your Vc which is 2Meg Ohm from datasheet. 

    It is generally advised that fzc is a decade below your cutoff frequency fc.

    Regards,

    Audison