I am a newbie power supply designer.
I have 44 mV of ripple (from my switching regulator) going into my linear regulator at f=1MHz. I have Cin=Cout=4.7uF. The linear regulator is not reducing the ripple. I tried adding small value caps at the output of the regulator.The input/output caps are very close to the regulator. The PSRR is about -40 dB at 1MHz at the desired current.
Any suggestions? I have used linear regulators in the past without a hitch; this is the first app that the noise has not been filtered.
This is also happening on a related part the ADP1755.
The LDO will only reject noise at 1MHz by about 10-40dB depending on how much headroom you have. Can you provide more information about the LDO input and output voltages?
You will probably also want to add a small ferrite bead in series with the output of the switcher to reduce the high frequency noise before it gets into the LDO.