I am using LT8582 as a SEPIC and Inverting pre-regulator (+-4.5V output), with linear post-regulators (LT3045/LT3094), following the layout guidelines of the datasheet (pages 16 and 18).
Noise is a considerable concern and the evaluation board (DC1734) has a different configuration (two fixed inductors instead of a coupled inductor; combining input and power capacitors)
- The recommended layout on page 18 (and 17) puts CPWR1, COUT1 and CPWR2, COUT2 directly on the edge of the LT8582.
- In the SEPIC layout, this reduces the loop area from switch to flying cap to diode to output cap to ground return.
- In the inverting layout, however, this increases the loop area from switch to flying cap to diode to ground return.
- My layout uses a coupled inductor (as on page 18 as well), and considering the inductors' size (12.5x12.5mm), this puts the capacitors CPWR1/CPWR2 on the SEPIC and on the inverting part far from the inductors L2/L3 (around 20mm) since it needs to be routed around the ground returns for the inductor resp. diode. Also, the output capacitor on the inverting configuration will be similarly far from the output.
- If I move CPWR1/2 away from the LT8582 and closer to the input of the inductors, this could reduce the loop area for the inverting regulator and follow the datasheet's guideline on placing the capacitor closer to the inductor, hopefully reducing the loop area from cap to inductor to switch. How would the ground return in this case be recommended to be routed?
- The guidelines do not mention to keep the ground path from the inductor (SEPIC) and from the diode (inverting) separate from the input capacitor's ground path, but I assume this would couple the switching noise to the input. Is this corrrect?
- Is there a recommended practice for using snubbers with the LT8582? An RC snubber across the flying capacitor would tightly fit the layout.
- Can the zone for the ground return for RT and SS be used for a bulk capacitor?