LT8582 Layout Questions & Review

I am using LT8582 as a SEPIC and Inverting pre-regulator (+-4.5V output), with linear post-regulators (LT3045/LT3094), following the layout guidelines of the datasheet (pages 16 and 18).

Noise is a considerable concern and the evaluation board (DC1734) has a different configuration (two fixed inductors instead of a coupled inductor; combining input and power capacitors)

  1. The recommended layout on page 18 (and 17) puts CPWR1, COUT1 and CPWR2, COUT2 directly on the edge of the LT8582.
    1. In the SEPIC layout, this reduces the loop area from switch to flying cap to diode to output cap to ground return.
    2. In the inverting layout, however, this increases the loop area from switch to flying cap to diode to ground return.
    3. My layout uses a coupled inductor (as on page 18 as well), and considering the inductors' size (12.5x12.5mm), this puts the capacitors CPWR1/CPWR2 on the SEPIC and on the inverting part far from the inductors L2/L3 (around 20mm) since it needs to be routed around the ground returns for the inductor resp. diode. Also, the output capacitor on the inverting configuration will be similarly far from the output.
    4. If I move CPWR1/2 away from the LT8582 and closer to the input of the inductors, this could reduce the loop area for the inverting regulator and follow the datasheet's guideline on placing the capacitor closer to the inductor, hopefully reducing the loop area from cap to inductor to switch. How would the ground return in this case be recommended to be routed?
    5. The guidelines do not mention to keep the ground path from the inductor (SEPIC) and from the diode (inverting) separate from the input capacitor's ground path, but I assume this would couple the switching noise to the input. Is this corrrect?
  2. Is there a recommended practice for using snubbers with the LT8582? An RC snubber across the flying capacitor would tightly fit the layout.
  3. Can the zone for the ground return for RT and SS be used for a bulk capacitor?
  • +1
    •  Analog Employees 
    on May 12, 2021 4:53 PM

    1.  A lot of thought has been put into the datasheet recommended layout. I recommend following it as close as possible. Ensure the Layer 2 GND plane is a solid plane with minimal spacing to layer 1 (IC layer). Coupled inductors are typically an advantage even if it adversely affects the layout. Input and out put cap placement is more forgiving on sepic and dual inductor inverting supplies because the inductors are between the switch and input and between switch and output.

    2. Snubbers across the flying cap should not be necessary with coupled inductors. You can protect for it if it doesn't adversely affect the layout.

    3.  SS and RT currents should not be shared with large currents.

  • Thank you so much for the fast response and hints! It puts my mind more at ease about following the datasheet. Is there a specific reason the evaluation board didn't go with that layout and e.g. fixed inductors? – I expected (3), but wanted to double-check since it would save some space in a dense layout.

  • 0
    •  Analog Employees 
    on May 13, 2021 2:16 PM in reply to ab2

    There could be many reasons why the demoboard didn't follow the datasheet guidance exactly. Reasons from availability of inductors to wanting to demonstrate independent inductors will also work to datasheet recommendation was after the demoboard layout. For best emi follow the datasheet recommendations.