LT4363 timer current and fault timing calculation.

Application and Circuit Description

We are using the LT4363-2 as an overvoltage and overcurrent protector in our products.

The design calculation and simulated values do not agree and hence want to confirm whether my calculations are correct. I suspect there is an error in my calculation since the simulated and experimental results closely agree. I also wish to clarify some data sheet specifications.

Design Parameters.

Output voltage            = Vout = 35.7V
Overvoltage                = Vov   = 38.25V
Undervoltage             = Vuv   = 8.5V
Overcurrent                 = Ioc    = 5A

The required component values were calculated based on the above design parameters.
Please refer the attached Mathematica worksheet and the LTspice circuit diagram.

For the calculation of the fault time, it is required to know the timer current ITMR through the timing capacitor CTMR. Based on the data sheet specifications the equation for the ITMR versus VDS during the overvoltage condition is given by, please refer the attached calculation notes.

ITMR = 0.61745 VDS + 3.69       (Note here VDS is in Volts and ITMR is in µA)

When the input voltage, VCC, is between 35.7V and 38.25V LT3643-2 will be in retry mode.
For the case when VCC = 38V, VCC – VOUT = 38V – 35.7V = 2.3V.
Since the load current is negligible VCC – VOUT = VD – VS = VDS = 2.3V.

Based on this VDS of 2.3V the calculated ITMR is 5.11µA.

For a 1µF timing capacitor the fault time, tFLT can be calculated to be 151ms.
This is the time taken for the timer capacitor voltage, VTMR, to rise from 0.5V to 1.275V.
Again please refer the attached calculation notes.

 

I have simulated the above design using LTspice and the following are the results.

Following do not agree with the calculation.
Simulated ITMR = 3.17µA during tFLT.
Simulated tFLT, VTMR, to rise from 0.5V to 1.275V = 243ms.

Calculated ITMR = 5.11µA during tFLT.
Calculated tFLT, VTMR, to rise from 0.5V to 1.275V = 151ms.

Implementation results.
Measured tFLT, VTMR, to rise from 0.5V to 1.275V = 230ms.PDFPDFLT4363IMS-2 ADI Engineer Zone.asc

 

Engineer Zone Questions.

  1. Based on the equation for ITMR it cannot go below 3.69µA during an overvoltage condition. Hence why does the simulation give a result of 3.17µA.
  2. According to the data sheet of LT4363, Revision F on page 11, once VTMR reaches a voltage of 1.275V the timer current ITMR is set to a fixed value 6µA. But the typical value of ITMR is 5µA as specified on page 4. The simulation also verifies that the ITMR 5µA as VTMR rises from 1.275 to 1.375V. Which is the correct fixed typical value for ITMR.
  3. According to the data sheet of LT4363, on page 12, during the overcurrent condition ITMR linearly rises form 8µA when VDS is 0.5V to 260µA when VDS is 80V. But on the graph Overcurrent TMR Current vs (VCC – VOUT) plot, on page 6, ITMR does not reach 260µA when VDS is 80V. But the typical value of ITMR is specified as 250µA when VDS is 80V on page 4.
    Note LT4356, a different but similar device, has an ITMR of 260µA as its typical value.
  4. The design example on page 17 of the data sheet has an ITMR of 45.5µA during an overcurrent event with an VCC of 14V. How was the above value determined?
    Based on a similar calculation during the overcurrent condition the ITMR equation is given by:
    (Note here VDS is in Volts and ITMR is in µA)
    ITMR = 3.17 VDS + 6.42 = 50.8 µA If ITMR 260µA when VDS is 80V
    or
    ITMR = 3.04 VDS + 6.48 = 49.1 µA        If ITMR 250µA when VDS is 80V

    Which is the correct typical value to use?

 

Thanks

Diva

  • Hi

    In the attached LTspice simulation circuit diagram R1 and R3 should be corrected as follows.

    R1 = 57k and R3 = 290k.

    Regards

    Diva

  • Hello Diva,  Your Itmr-ov equation seems to overestimate Itmr for low Vds, e.g., at 10Vds it gives 9.9uA whereas graph on datasheet page 6 shows ~8uA. Please use the typical numbers from the Electrical Characteristics table on datasheet pages 3 and 4. More importantly, the Itmr specification shows that it can vary by 20% to 50% depending on the condition. If using typical numbers to derive timer capacitor, always keep it adjustable on the board. Lastly, it is better to set the retry inhibit threshold (OV pin) in between your supply maximum operating voltage and the output clamp voltage (35.7V) so that LT4363 doesn't keep retrying indefinitely for an invalid supply voltage. For further questions specific to your design, please submit a Technical Support Request: form.analog.com/.../techsupport.aspx