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Question about θja of LTC4020

Hello,

Would you let me know the conditions about  the θja of LTC4020 (34C/W) ?

PCB layer:

Cu thickness: 1OZ or 2OZ?

GND area for cooling:

I'm going to make a trial board using 2 layers but I need to know 2 layer board is feasible regarding thermal issue..

My spec is Vin=50V, Vbat_setting=40V, Icharge=5A

Regards,

Kazu

Parents
  • Making an LTC4020 board with only 2 layers will be challenging.  It is difficult to include SGND and PGND planes with only 2 layers. 

    2oz. (71µm) copper is preferred for thermal and electrical conductivity.

    The main source of heat in the LTC4020 is the internal regulator which regulates the INTVCC voltage (5V) from the input voltage at PVIN.  See the discussion in the datasheet, pp. 25, 26.  You can reduce this power dissipation by using low-Qg FETs in the power stage.  If power dissipation is still outside the SOA curve in figure 8 you should include a linear pre-regulator for PVIN.  (Note that the power-limit portion of the SOA curve corresponds to 0.5W.)  An external regulator such as the LT3012-DE can be set up for 6V output which can drive the PVIN input.  Note: Do not use the circuits in figure 9, 10 of the datasheet.  They will not work reliably.

Reply
  • Making an LTC4020 board with only 2 layers will be challenging.  It is difficult to include SGND and PGND planes with only 2 layers. 

    2oz. (71µm) copper is preferred for thermal and electrical conductivity.

    The main source of heat in the LTC4020 is the internal regulator which regulates the INTVCC voltage (5V) from the input voltage at PVIN.  See the discussion in the datasheet, pp. 25, 26.  You can reduce this power dissipation by using low-Qg FETs in the power stage.  If power dissipation is still outside the SOA curve in figure 8 you should include a linear pre-regulator for PVIN.  (Note that the power-limit portion of the SOA curve corresponds to 0.5W.)  An external regulator such as the LT3012-DE can be set up for 6V output which can drive the PVIN input.  Note: Do not use the circuits in figure 9, 10 of the datasheet.  They will not work reliably.

Children
  • Hello WATaylor-san,

    Thank you for the prompt reply.

    Some trial boards with 2 layers were already made and the temp of the LTC4020 goes up to more than 100 degC. (Even almost no charge current, package temp goes up to 60 to 70degC)

    I have to reduce the temp rising following your latest reply but I think it's difficult to do it with 2 layer board.

    I have two questions in the attachment. I hope to hear from you soon.

    PDF

    Regards,

    Kazu

  • For the calculation of INTVCC current you should use the total gate charge number for VGS=4.5V.  Calculation with Qg=33nC will give 33mA for P(INTVCC)=(45V-5V)*33mA=1.32W which is still too high according to the SOA curve in the datasheet.  I do not recommend exceeding 500mW dissipation in the INTVCC regulator.  If you are not able to add a 6V preregulator to the PVIN you should look at using FETs with lower total gate charge.  For example, you should be able to find 60V FETs with the same on resistance that will require less total gate charge.

    With Vin=45V and Vbat=40V FET C will be off most of the time.  Also, the current in FET B will be much lower than the current in FET A.  You should be able to use 60V FETs with higher RDS(ON) and lower gate charge for FETs B and C.

    To summarize, you must find a solution to reduce the power dissipation in the INTVCC regulator.  A 4 layer board will give better thermal performance of the entire circuit, but it will not solve the heating problem within the LTC4020.  Also, a 4 layer board will allow you to create an SGND plane (with signal-level currents only) and connect SGND to a PGND plane at only one point.  For example, in the layout for the DC2044A demo board PGND (pin 35) and SGND (pins 3, 29) are connected only at the LTC4020 pad.

  • Hello WATaylor-san,

    Due to board size constraints, it seems difficult to add a 6V preregulator. I will try to improve it by changing to FETs with lower Qg and the number of board layers.

    I have a question.
    What are the approximate board conditions for a thermal resistance of 34 °C/W?

    I would like to know at least a rough estimate of how much heat dissipation area is needed.

    Regards,

    Kazu