ADM1272 short circuit and EFAULT level and behavior

Dear ADI Expert,

My customer has 2 questions about the ADM1272 short circuit and EFAULT level and behavior. 

1. ADM1272 not only detects Vsense when the output is short-circuited but also detects VDS, right? How much VDS voltage will be judged as output short by ADM1272?

2. The ADM1272 datasheet writes that the EFAULT pin reaches 1V and the FET will be turned off. My customer increases the current by E-load to test OCP. The FET will not turn off until EFAULT reaches 1.78V(As below in picture1 & 2). Why is it not 1V? Why is it very different from the calculation tool?




Best regards.

Andy Yang.

  • 0
    •  Analog Employees 
    on Apr 19, 2021 4:24 PM

    Hi Andy,

        The ADM1272 distinguishes between OC and severe OC events strictly by measuring current (voltage across Rsense), and not using Vds. When there is a short circuit at the output the ADM1272 detects the very large current (> 2x the ISET OC limit) and reacts within <500ns by pulling down the FET gate, forcing Vgs to 0V. Because it detects current the ADM1272 can react very quickly to faults, without waiting for Vds to change.

        The ADM1272 DOES use Vds during normal OCP events, when current is less than the severe overcurrent limit. In these cases the FET gate is controlled to limit current for a period of time dictated by the EFAULT pin, which is a timer function. The EFAULT pin outputs a current proportional to Vds across the FET, and so ramps up more quickly if the FET is under larger stress, and more slowly for smaller Vds stress. When the EFAULT pin ramps up above 1V the FET turns off. There is a 32us filter on the EFAULT pin, so when the pin voltage exceeds 1V the delay forces an additional time before turning off the FET.

        In most cases it is not practical to design a circuit that relies on very fast response at the EFAULT pin. I see that you have chosen 2.2nF as you capacitor on the EFAULT pin, which produces extremely short delays when Vds is >10V. While this may seem necessary to protect the FET, remember that during "normal" OCP events the Vds across the FET remains small because the gate moves relatively slowly, so FET stress is limited. Since the FET Rdson remains low until Vgs approaches Vth current can continue to rise without harming the FET, and the current will easily exceed the severe overcurrent limit well before the FET experiences significant stress. There are relatively few events where the load causes FET Vds to linger at a large value for any length of time. If there are use cases where the FET will be destroyed in less than 100us you need to choose a better FET (better SOA).