adp2323 emi and snubber design

I am using the ADP2323 for one of our designs and i can see low amplitude spikes (10mVpp) at the switching frequency on some board outputs (on clock signals ). I was wondering if an RC snubber circuit at the output MOSFET could help reduce these spikes leaking into sensitive sections of the board.

I see that the ADP2323 evaluation board has provision for RC snubber (R6, C11 and R20, C14) but is not populated. Is there any reference for optimal RC values that can be calculated for APD2323 ? I would appreciate any inputs.

Thanks.

AB

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    •  Analog Employees 
    on Oct 22, 2014 4:25 AM

    If there is enough GND layer around the part then having a single GND for the system should be ok but... the key for power supply designs to guarantee they do not inject noise into the GND plane is to connect the 3 main high current ground paths of each channel together and on the same layer.

    In you case:

    Q1GND, C24 and C23 GND side need to be very close together and ideally on the same layer.

    same is valid for the other channel

    Q2GND, C26 and C18 GND side need to be very close together and ideally on the same layer

    Also the drain of Q1 and Q2 need to be very close to the respective SW pins.

    If you post or email me the layout I can take a look.

    Another thing to scrutinize is the inductor L1 to make sure if has good shielding. Not all shielded inductors performs the same. What's the PN of the one you are using?

    Best Regards,

    LucaV

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  • 0
    •  Analog Employees 
    on Oct 22, 2014 4:25 AM

    If there is enough GND layer around the part then having a single GND for the system should be ok but... the key for power supply designs to guarantee they do not inject noise into the GND plane is to connect the 3 main high current ground paths of each channel together and on the same layer.

    In you case:

    Q1GND, C24 and C23 GND side need to be very close together and ideally on the same layer.

    same is valid for the other channel

    Q2GND, C26 and C18 GND side need to be very close together and ideally on the same layer

    Also the drain of Q1 and Q2 need to be very close to the respective SW pins.

    If you post or email me the layout I can take a look.

    Another thing to scrutinize is the inductor L1 to make sure if has good shielding. Not all shielded inductors performs the same. What's the PN of the one you are using?

    Best Regards,

    LucaV

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