Paralleled LTC4367 for redundancy

Hi ADI expert

I have a application that needs two LTC4367 as an Or-ring but connects to the same power source

why I need to do this is not for current sharing but redundancy. 

May I know if there is any side effect of the architecture?

I think the current of the paths may not be 100% balanced but it's not a critical issue to me

please see my system functional block as below:

thanks

Ken



add description
[edited by: Kencheng at 1:47 PM (GMT -5) on 19 Feb 2021]
Parents
  • +1
    •  Analog Employees 
    on Feb 19, 2021 7:36 PM

    One potential issue is at turn-on: don’t assume SOA is shared.

    Let’s say VIN is increased from 0V to whatever the nominal UV value is. One of the channels will conduct before the other, due to variance in the resistors, pin leakage, UV threshold voltage, and threshold voltages of the FETs. This means one channel may have to charge the output capacitance up to the UV level on its own; we shouldn’t assume that the stress from turn-on will be shared equally, or at all.

    So worst case, one of the FETs (M1) takes all the stress of charging the output cap. I see in your diagram there is no inrush control. I recommend that you add an RC to the gate pin to control the amount of inrush current that charges the output cap (see page 15 for sizing CGATE ; RGATE=5.1kΩ). Otherwise, the only thing limiting current would be the ESR of the cap and how much current VIN can supply.

    Once you add inrush control, you’ll know the amount of current charging the output cap, the voltage the cap is being charged to, and you can calculate how long it takes to charge the cap. Now take this current, voltage, and charge time, and open the datasheet of the FET and check the SOA graph. See if the FET can survive turn-on stress. It probably won’t have the same time curve as you, but it should have something close enough for you to make a judgement call.

    Hope this helps,
    -Aaron

Reply
  • +1
    •  Analog Employees 
    on Feb 19, 2021 7:36 PM

    One potential issue is at turn-on: don’t assume SOA is shared.

    Let’s say VIN is increased from 0V to whatever the nominal UV value is. One of the channels will conduct before the other, due to variance in the resistors, pin leakage, UV threshold voltage, and threshold voltages of the FETs. This means one channel may have to charge the output capacitance up to the UV level on its own; we shouldn’t assume that the stress from turn-on will be shared equally, or at all.

    So worst case, one of the FETs (M1) takes all the stress of charging the output cap. I see in your diagram there is no inrush control. I recommend that you add an RC to the gate pin to control the amount of inrush current that charges the output cap (see page 15 for sizing CGATE ; RGATE=5.1kΩ). Otherwise, the only thing limiting current would be the ESR of the cap and how much current VIN can supply.

    Once you add inrush control, you’ll know the amount of current charging the output cap, the voltage the cap is being charged to, and you can calculate how long it takes to charge the cap. Now take this current, voltage, and charge time, and open the datasheet of the FET and check the SOA graph. See if the FET can survive turn-on stress. It probably won’t have the same time curve as you, but it should have something close enough for you to make a judgement call.

    Hope this helps,
    -Aaron

Children
No Data