Design with ADP2325

Hello,

 

My name is Meir and I am DFAE at Phoenix technologies in Israel.

 

Silicom, one of my customers, started to evaluate the ADP2325 and ADP5023.

They are using the ADIsimPOWER and we have some questions regarding the results that we have got from this tool.

  1. The tool recommends to use peripheral components size of 0805 as shown in Figure1 in attached file. Although, according to user guide recommended BOM - peripheral parts size – 0603 as shown in Figure2 in attached file
    1. What is the reason for using this size of parts?
    2. Their design is very high density and small size is very critical for them. Can they use the 0402 size components?

 

  1. What is the GND connection recommendations?
    1. Accorrding to the data sheet, single GND required (as shown in Figure3 in attached file).
    2. According to the ADIsimPOWER tool, the GND is separated (as shown in Figure4 in attached file)
    3. Appreciate if could you send us the GNDs connection recommendations and layout guidelines.

 

  1. According to the ADIsimPOWER tool, ZENER diode shall be optional connected on Vout. I suppose that this diode is intended for high voltage protection, is it? (as shown in Figure5 in attached file)
    1. Is my customer can remove this part from the design? This part is not connected in data sheet.

 

 

Additional info regarding the customer’s power configuration in attached file.

 

Thanks,

Meir

attachments.zip
Parents
  • 0
    •  Analog Employees 
    on Mar 12, 2015 10:01 PM over 6 years ago

    Hi Meir,

    Thanks for using ADIsimPower Design Tools.

     

     

    Yes you can use 0402 or 0603 or 0805 package for the signal components, the tool uses 0805 for easy board building. Size matters only for the power components like the bias capacitors and inductors, FETs as they will affect the functional capacitance and power dissipations and so on. If compact design is preferred, you could select design for Small Size from the Basic User Input. The tool will provide you solution optimized for size. You could also choose the desired inductor, input /output caps, FETs from the hyperlinked items in the BOM.

    We used different symbols for AGND and PGND in the tool for guiding a low noise layout. The key to the power supply layout is keep the high current path as short as possible and covers as less area as possible. Connect the high current ground paths of each channel together and on the same layer to avoid noise injecting to other GND plane.  For example. Cin1a GND and Cout1a GND and Q1a GND side need to be very close together, the Drain of Qia need to be as close as possible to corresponding SW pin of the IC. The same rule apply for the 2nd channel. In the design tool, if you go to “Build this Design” page, you can see the layout picture for the tool Eval Board. And here is another reference for the ADP2323 layout: http://www.analog.com/media/en/technical-documentation/user-guides/UG-310.pdf

     

    In the design tool, the Diode provide an option for asynchronous design where FETs re not used. In the BOM you attached ou can see that D1a and D1b is not used.

    Best regards,

     

    Hong

     

Reply
  • 0
    •  Analog Employees 
    on Mar 12, 2015 10:01 PM over 6 years ago

    Hi Meir,

    Thanks for using ADIsimPower Design Tools.

     

     

    Yes you can use 0402 or 0603 or 0805 package for the signal components, the tool uses 0805 for easy board building. Size matters only for the power components like the bias capacitors and inductors, FETs as they will affect the functional capacitance and power dissipations and so on. If compact design is preferred, you could select design for Small Size from the Basic User Input. The tool will provide you solution optimized for size. You could also choose the desired inductor, input /output caps, FETs from the hyperlinked items in the BOM.

    We used different symbols for AGND and PGND in the tool for guiding a low noise layout. The key to the power supply layout is keep the high current path as short as possible and covers as less area as possible. Connect the high current ground paths of each channel together and on the same layer to avoid noise injecting to other GND plane.  For example. Cin1a GND and Cout1a GND and Q1a GND side need to be very close together, the Drain of Qia need to be as close as possible to corresponding SW pin of the IC. The same rule apply for the 2nd channel. In the design tool, if you go to “Build this Design” page, you can see the layout picture for the tool Eval Board. And here is another reference for the ADP2323 layout: http://www.analog.com/media/en/technical-documentation/user-guides/UG-310.pdf

     

    In the design tool, the Diode provide an option for asynchronous design where FETs re not used. In the BOM you attached ou can see that D1a and D1b is not used.

    Best regards,

     

    Hong

     

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