How to setting or calculation the ADM1278 output current ramping up rate?

Dear ADI Expert,

How to setting or calculation the ADM1278 output current ramping up rate? My customer uses the following circuit. The end customer has a requirement. "Current ramping up rate at starting up transient of 12V rail should be limited within 0.05A/us". I can't find this in the Datasheet or Design Guide. Only SETTING A LINEAR OUTPUT VOLTAGE RAMP AT POWER UP. No OUTPUT CURRENT RAMP AT POWER UP.

Thanks.

Best regards.

Andy Yang.

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  • 0
    •  Analog Employees 
    on Feb 23, 2021 5:05 PM 1 month ago

    Hi Andy,

        The ADM1278 does not set a CURRENT ramp. It sets a linear VOLTAGE ramp, which charges the output capacitors at a constant current, as explained in the datasheet section "SETTING A LINEAR OUTPUT VOLTAGE RAMP AT POWERUP". Figure 55 shows a capacitor attached to the gate of the FET. Set the size of this capacitor to limit the dv/dt of the GATE node, which also sets the dv/dt of the FET source (is is a source follower). In your schematic this is PC424. This is the recommended use for the ADM1278, and you should consider starting in this mode.

        You may be able to set a suitable current ramp using the PSET limit, which imposes a POWER restriction on (Vds * I) in the FET, so as Vds decreases while the output is ramping the allowed current will increase proportionally. You will have to be careful to set the TIMER value very long in order to prevent timeout while ramping the output. Note that you will also need to be careful to stay within the SOA of your FETs when operating with a long timer value. If you use the design spreadsheet tool it will warn you that PSET dominates startup.

    Thanks!

      Nathan

Reply
  • 0
    •  Analog Employees 
    on Feb 23, 2021 5:05 PM 1 month ago

    Hi Andy,

        The ADM1278 does not set a CURRENT ramp. It sets a linear VOLTAGE ramp, which charges the output capacitors at a constant current, as explained in the datasheet section "SETTING A LINEAR OUTPUT VOLTAGE RAMP AT POWERUP". Figure 55 shows a capacitor attached to the gate of the FET. Set the size of this capacitor to limit the dv/dt of the GATE node, which also sets the dv/dt of the FET source (is is a source follower). In your schematic this is PC424. This is the recommended use for the ADM1278, and you should consider starting in this mode.

        You may be able to set a suitable current ramp using the PSET limit, which imposes a POWER restriction on (Vds * I) in the FET, so as Vds decreases while the output is ramping the allowed current will increase proportionally. You will have to be careful to set the TIMER value very long in order to prevent timeout while ramping the output. Note that you will also need to be careful to stay within the SOA of your FETs when operating with a long timer value. If you use the design spreadsheet tool it will warn you that PSET dominates startup.

    Thanks!

      Nathan

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