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LTC3112 LTspice FRA simulation

To find the phase margin in the circuit, I ran LTspice FRA simulation.

I used component values of power stage and compensation network  in Loop Compensation Example in the datasheet.

But, I got the simulation below

Please teach me what was the cause of the problem?

I also attached simulation file.

LTC3112.asc

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  • Hi,

    Are you looking to check the stability of the design with the FRA simulation. I was not able to simulate the spice model you shared. But seeing the gain of the bode plot you shared it looks like the crossover freq is very high and might not be stable. It is indeed one of the way to do but I wont rely on the results as the model gets complicated it might be very accurate. Instead it is recommended to get the bode plot of the loop gain using the transfer function given in the datasheet. Also you could do load step during the transient analysis and check if the step response is good enough. 

    Thanks

Reply
  • Hi,

    Are you looking to check the stability of the design with the FRA simulation. I was not able to simulate the spice model you shared. But seeing the gain of the bode plot you shared it looks like the crossover freq is very high and might not be stable. It is indeed one of the way to do but I wont rely on the results as the model gets complicated it might be very accurate. Instead it is recommended to get the bode plot of the loop gain using the transfer function given in the datasheet. Also you could do load step during the transient analysis and check if the step response is good enough. 

    Thanks

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