Regarding MPS support of LT4295


Regarding LT4295, I have the following two questions, and could you give me some advice?

①Can the LT4295 support short MPS?
②There is an IMPS at the end of the electrical characteristics of the LT4295 datasheet.
Is it correct to understand that this IMPS is constantly consumed by the LT4295 and meets the MPS requirements issued by the PSE?

Thank you for your help.

  • 0
    •  Analog Employees 
    on Jan 20, 2021 10:10 AM 2 months ago

    Hello NEK:

    without being an expert for PoE my inputs woul dbe as follow:

    1. Do you mean the defined timing limits with 'short' MPS?

    2. The LT4295 sinks the MPS current constantly, hence this would put a 'no' to your answer 1. And yes, this behaviour is intentional to follow the standard.

  • 0
    •  Analog Employees 
    on Jan 20, 2021 10:21 PM 2 months ago in reply to MarkusHP

    Hey Markus, NEK,

    The quick answer is that Short MPS is not implemented by default by the LT4295. And the LT4295 does not draw IMPS constantly. The LT4295's DC-DC converter's quiescent current satisfies the MPS requirement. This means there is no need to draw an additional MPS current while the isolated DC-DC converter is operating.

    The Maintain Power Signature can either be DC or pulsed current, 10mA for Class 4 and lower and 16mA for Class 5 and higher. IEEE 802.3af/at allows for the PD to draw the MPS current for a minimum of 75ms followed by no current drawn for no longer than 250ms. All PDs, including the LT4295 are allowed to draw MPS at roughly a 30% minimum duty cycle.

    Short MPS is new to IEEE 802.3bt and it is supported by Type 3 and Type 4 PSEs. It reduces the MPS signature to 7ms of current draw with 310ms dropout, roughly a 2.3% duty cycle. Care must be taken when implementing Short MPS near its minimum duty cycle. The LT4295 does report the width of the first Class event to differentiate between lower power Type 3 PSEs and Type 1 / Type 2 PSEs. Short MPS may be implemented discretely if a Type 3 or Type 4 PSE is identified. The LT4295 reports allocated power via its T2P pin.

    IMPS specified in the electrical characteristics refers to a feature brought over from the LT4276, but no longer discussed in the LT4295 datasheet. The IEEE 802.3bt standard requires the PD to wait 80ms after power on before drawing full load. IMPS is only drawn after inrush is completed and while the tSTART timer is running during the delayed start.

    Best Regards,


  • >The LT4295 does report the width of the first Class event to differentiate between lower power Type 3 PSEs and Type 1 / Type 2 PSEs.

    At which terminal can I check it?
    If I want to request a Class 4 PD and I don't know if I've connected to a Type-3 PSE or a Type-2 PSE, I'm not sure if I can enable short MPS.

    Thank you.

  • 0
    •  Analog Employees 
    on Feb 9, 2021 1:41 AM 2 months ago in reply to Imayan

    The T2P pin indicates physical layer power allocation. For your example of a Class 4 PD, since the power allocations between a Type 3 and Type 2 PSE are the same, the T2P pin state is the same. Your application may be able to use the link layer discovery protocol (LLDP) to determine if the PSE is Type 3 or Type 4, then it could enable short MPS.

    Best Regards,


  • Thank you for your reply.

    OK , I understand T2P and LLDP.

Reply Children
No Data