ADM1272 design question

andyyang@arrowasia.com on Jan 8, 2021

Dear ADI Expert,

My customer designed the ADM1272 circuit according to ADM1272-DESIGN-GUIDE-GENERAL-181015.pdf. Just place a similar RC network on the EFAULT pin in the picture below.

The ADM1272_Workbook tool needs the bottom resistor(R18).

My customer wants to know if the bottom resistor (R18) is necessary? What is the risk if there is no that bottom resistor (R18)? How to calculate if there is no that bottom resistor (R18)?

The customer working conditions: Vin=54V, PSMN4R8-100BSE x4, Imax continue=under 50A, OCP=95A. When the customer first started designing, I told the customer that 4 PSMN4R8-100BSE cannot handle OCP=95A. But the customer still does this and mass-produces the circuit shown in the picture below. What are the risks of this circuit?

Thanks & best regards.

Andy Yang.

0 nenger

on Jan 8, 2021 8:45 PM
Hi Andy,

    The bottom resistor serves two purposes. First, it adjusts the very slow timing of the RC circuit, allowing you to optimize the time that the FET is allowed to remain in current limit for small Vds voltage (lower stress). Second, it creates a path for current to bleed off of the capacitor, allowing it to discharge when the FET exits stress condition and begins cooling again.

    There are no severe risks to omitting the bottom resistor. The RC circuit will be overly pessimistic in estimating FET stress, and will turn off earlier than it would with the bottom resistor in place.

    In the spreadsheet tool you can approximate having no bottom resistor by setting the value of R18 to 10^7 or higher.

Thanks!

Nathan
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0 andyyang@arrowasia.com on Jan 12, 2021 5:44 AM in reply to nenger

Dear Nathan,

Thanks for the explanation. My customer wants to know how to measure/check the delay time. Which signal or pin can measure/check the delay time?

Thanks & best regards.

Andy Yang.
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0 nenger

on Jan 12, 2021 7:17 PM in reply to andyyang@arrowasia.com
Hi Andy,

As with simpler hotswap circuits that have a TIMER pin, the EFAULT pin has a logic threshold, and rises up to reach that threshold, after which the FET turns off and the FAULTb pin is asserted. You can measure the time that it takes for the EFAULT pin to rise up to 1.0V, and also look at the FAULTb pin, which should assert about 30us later. These measures will show you the timing behavior of both the EFAULT and ESTART pins.

Thanks!

Nathan
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