I am using the LT3021ES8 to generate a fixed bias voltage for a power amplifier MOSFET and am seeing a lot more variation in the output voltage than I want or expect. I am shooting for an output voltage of 693 mV +/- 2 mV, but am seeing output voltages from 689 mV - 699 mV. I am using resistors in the feedback network with a 0.5% tolerance and a low thermal coefficient (25 ppm/C). The only measurement I can get to correlate is the voltage seen on the ADJ pin. From the datasheet, this voltage should be 200 mV at room temperature with a variation of maybe 0.1 mV over temperature, per the ADJ Pin Voltage plot on page 6 of the datasheet. However, I am measuring ADJ pin voltages from 199.40 mV - 202.15 mV, the variation which directly correlates with the variations in the output voltages seen in my regulator circuits. So why is this happening? I am not expecting this much variation.
I'm uploading a picture of the circuit schematic, where the Vg_1 voltage on the output of the regulator circuit feeds the gate of a power amplifier MOSFET (not shown). However, I am currently testing the circuit without the MOSFET attached, using just the circuitry shown in the uploaded image. Since the expected load is very capacitive, there is a 300 pF capacitance in parallel with the upper voltage divider resistor, as specified in the datasheet. Also, since the MOSFET gate load draws no current, there is a 6.8 kOhm resistor load to draw the suggested minimum 100 uA of current to insure stability. Both of which are per the Output Capacitance and Transient Response section on page 10 of the datasheet.
Here is the circuit: