Figure 13 in the data sheet implies the /INT output (via EVENT_INT) deasserts when the FIFO is empty but that isn't the behavior I observe. My code monitors when /INT goes low then reads the event count register then reads that many FIFOs. But even though I empty the FIFO, I then have to specifically clear EVENT_INT by writing 0x01 to register 0x01. What's disturbing is this write operation even deasserts /INT when the FIFO is not empty, possibly causing my code to miss an event. How should I configure and interpret the registers so I can't miss or accidentally dump a key event in the FIFO based on monitoring the /INT signal?