I'm a DFAE in Japan. Our customer has a question. When the SET pin of LT3082 is disconnected from RSE and CSET, I think the OUT pin is Hi-Z. Is it correct?
I think your customer noticed that SET acts strangely in the LT3082 LTspice simulation when SET is OPEN. I show the strange behavior in the image below of my simulation circuit and the simulation results. The simulation is correct when it shows the output current will shut off when OUT goes above VIN - VDROPOUT, but VSET should not go to a voltage that is higher than VIN. The model should show that SET also cannot go higher than VIN-VDROPOUT. When SET is OPEN, VSET should clamp to the lower of VOUT + VF or VIN - VDROPOUT. Thank your customer for letting us know. I will report the bug in the LTspice model.
Thank you for the question. When the LT3082 is in current limit, the LT3082 acts like a current source. You can load a current source with an ideal voltage source. I sweep my ideal voltage source connected to OUT to show that the current turns off when VOUT is greater than VIN - VDROPOUT. Let me check the actual hardware and I will post again.