LT3082 Set pin open

Hi

I'm a DFAE in Japan. Our customer has a question. When the SET pin of LT3082 is disconnected from RSE and CSET, I think the OUT pin is Hi-Z. Is it correct?

Regards,

Hiroyuki

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  • 0
    •  Analog Employees 
    on Dec 22, 2020 4:01 PM

    I think your customer noticed that SET acts strangely in the LT3082 LTspice simulation when SET is OPEN.  I show the strange behavior in the  image below of my simulation circuit and the simulation results.  The simulation is correct when it shows the output current will shut off when OUT goes above VIN - VDROPOUT, but VSET should not go to a voltage that is higher than VIN.  The model should show that SET also cannot go higher than VIN-VDROPOUT.  When SET is OPEN, VSET should clamp to the lower of VOUT + VF or VIN - VDROPOUT.  Thank your customer for letting us know.  I will report the bug in the LTspice model.   

    LT3082 sim ckt and result_2.png

Reply
  • 0
    •  Analog Employees 
    on Dec 22, 2020 4:01 PM

    I think your customer noticed that SET acts strangely in the LT3082 LTspice simulation when SET is OPEN.  I show the strange behavior in the  image below of my simulation circuit and the simulation results.  The simulation is correct when it shows the output current will shut off when OUT goes above VIN - VDROPOUT, but VSET should not go to a voltage that is higher than VIN.  The model should show that SET also cannot go higher than VIN-VDROPOUT.  When SET is OPEN, VSET should clamp to the lower of VOUT + VF or VIN - VDROPOUT.  Thank your customer for letting us know.  I will report the bug in the LTspice model.   

    LT3082 sim ckt and result_2.png

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