ADP5061/62 battery isolation FET


(1) battery isolation

Vin = 0V (VBus not connected)

Vbat > Vweak (system is running from battery)

is it possible to isolate the battery from the system load by setting the EN_CHG & DIS_LDO bit via I2C --> total system shut down leading to minimum battery load (5µA right?)? Am I right that DIS_LDO will be reset after Vbus has been connected automatically and so the system would be powered in LDO mode in case Vbus is connected? We are planning to have a fixed soldered internal Lipo cell ... for that we would need the battery isolation/total system shut down (even if VBat>>Vweak) for maximum battery life time (during stock, ...)

(2) SYS_EN

what means 'active' in your datasheet:

- FET==active --> pin pulled low


- active means FET is open and pin is pulled high

is there a SYS_EN mode where SYS_EN is 'active' when Vin>Vin_ok OR Vbat>Vweak (usb connected or good battery) and deactivated if Vin<Vin_ok AND Vbat<Vweak (no usb and low battery) --> if yes (which mode?) I could use SYS_EN to en/disable a buck converter generating the system working voltage (2.7V)?

I have already ordered the eval board but you could help a lot in advance