About estimating duty cycle

Tarzan,

A more correct estimate of duty cycle is (Vout/Vin)*(1/e) where e is the efficiency factor.

Energy will be lost in the series resistance of the inductor (Vin must stay applied longer to achieve the same current ramp as for an ideal inductor.)  Channel resistance in the switching FETs, plus the DF of the output capacitor(s) also detract from the overall efficiency.

The datasheet for your regulator should have an efficiency vs output current plot that can provide you a good starting point for including 1/e in your initial design calculations.  Actual efficiency depends on many factors. Highly complex models in a Spice simulator can get pretty close, but to know the actual value usually relies on measurements taken from the actual implementation. Consider also that the actual value will not be a constant, but will vary depending on the load current.

Based on your calculated D = 0.55 and your measured D=0.646, you can assume the efficiency is ~85.1%.

Hope this helps.

Hi MBrookes,

Thank you for your answer!

I really appreciate it.

Best regards,

Tarzan

I think I am also facing this issue....  Any suggestion?

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