My customer designed a PLL board using HMC830 and HMC1060.
But, she has a problem that is randomly degraded the phase noise of HMC830 for a short time.
She has a few questions about HMC1060 design for HMC830 power.
1. What function is the resister(R39, R40) on VR1 and VR2 output in HMC830 EVB schematic ?
If the resister is removed is there any problem ?
2. In the above schematic, if she uses in combination with VR2 and VR3 by connecting between JP3 and JP4.
Is it possible application ?
3. She found out that inactivation of PTAT mode is recommended in the following configuration.
If she used PTAT mode in the following configuration Is there any problem ?
Have they may have some relevance to the above phase noise error ?
Thanks in advance.