Can I drive the EN/UVLO pin with LVCMOS 3.3V logic from an FPGA? Before configuration, the FPGA I/O will either be high impedance or weak pull-down. Then after configuration, the I/O will be driven high to enable the regulator. Also, if I were to use resistors R1, R2 to program UVLO, what resistor values do you recommend (VOL = 0.4 V max, VOH = 2.9 V min, IO = 4 mA max)?
Hi,
Yes you can use the 3.3V logic to enable the LDO.
As for the resistor values, refer to Page 18 of the Datasheet (https://www.analog.com/media/en/technical-documentation/data-sheets/ADP7104.pdf) for calculation of R1 and R2:
VOL = 0.4V max
VOH = 2.9V min
Vhys = 2.9V - 0.4V = 2.5V
R1 = Vhys / 10uA = 2.5V / 10uA
R1 = 250kOhm
R2 = 1.22V x R1/(VOH - 1.22V) = 1.22V x 250kOhm / (2.9V - 1.22V)
R2 = ~182kOhm
Regards,
Bryan
