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Drive ADP7104 EN/UVLO with Digital I/O

Can I drive the EN/UVLO pin with LVCMOS 3.3V logic from an FPGA? Before configuration, the FPGA I/O will either be high impedance or weak pull-down. Then after configuration, the I/O will be driven high to enable the regulator. Also, if I were to use resistors R1, R2 to program UVLO, what resistor values do you recommend (VOL = 0.4 V max, VOH = 2.9 V min, IO = 4 mA max)?

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