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How does the adp1046 keep zero crossing.

Right now we are testing HB LLC converter based on adp1046 CPU.

We had observed spikes on the secondary side while adp1046 changes frequency to keep needed output voltage.

While frequency is steady spikes absent.  We consider that the periodical zero crossing failure causes spikes.

The question is how does CPU follow the actual zero crossing during control process?

How important is the digital filters adjustment in GUI (currently we are in default  setting)?


  • Hi,

    What PWMs are you using to control the SR edges. If you are using SR1 or SR2 you have to adjust the dead time by moving the rising edge of SR1 and SR2 to the right by approximately 50-100ns based on typical data. The spikes are occurring due to non ZCS conduction of the SR fets. The easiest way, but may not be the most convenient, is to put a current probe on the secondary side and time the SR edges accordingly. You can refer to the waveforms figures 41-44 in UG-768 as an example. 

    For digital filter setting they are very important as they ensure the stability of your closed loop converter. You'll have to do a bode plot of the power supply and determine the phase margin and crossover frequency. Alternately if you don't have a network analyzer that does this you can check the transient response and check for potential oscillations, how fast is the settling time, under/over damped response etc.

    Lt Comm Data.

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