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ADM1270

Hi,

I want to limit the current using foldback function only. What I need to know is how to calculate the knee of the foldback current and the short circuit current.

My application is for 1 Amp @ 45V. Also, I didn't clearly understand exactly how to calculate the sense resistor value. I would appreciate if you could show some examples.

Thanks,

Kali

  • Hi Kali,

        I suggest that you take a look at the ADM1270 Design Worksheet Tool located on the ADM1270 Product page.

    www.analog.com/.../adm1270.html

        The tool will help you make design decisions for your ADM1270. Much of what you need to take into account has to do with FET parameters like Rdson, SOA, and Tj-max.

        For your specific questions:

    Choose a sense resistor that gives you the correct Vsense (50mV for default ISET) when Id = 1.2A (your load + margin). Remember to size the physical resistor large enough to dissipate the heat that it generates.

    Use datasheet fig 27 and 28 if you need to visualize the ISET and FLB current limits. Fig 37 shows how these current limits interact with each other. The "knee" in the curve is the point at which Vds across the FET causes the FLB voltage to fall below Viset/2. If you use the default ISET by tying ISET to VCAP then Viset defaults to 2V.

    Thanks!

      Nathan

  • Hi,

    Thank you very much for your quick response. I appreciate your detail explanation. This information is very helpful. I have one other question.

    In our application when the output load is shorted, power supply shouldn't shutdown. Power supply could provide minimum power and stay alive until the short is removed, recover automatically without any reset.

    Is it possible to disable the timer function? We just want to use the Foldback function only to limit the current.

    Thanks,

    Kalai

  • Hi Kali,

        The ADM1270 does not have a setting to disable the TIMER function. It exists to keep the FET safe, as every FET has its thermal limits, given by the SOA plot in the datasheet. You can use a very large capacitor on the TIMER pin in order to extend the time-out, but I do not recommend disabling it entirely (by shorting the TIMER pin to GND, for example). Any number of fault scenarios could cause the FET to operate in high stress and to fail if you let the condition persist indefinitely.

        If you want to experiment with what can happen when TIMER is disrupted, I suggest replacing the timer capacitor with a low value resistor. When you test the circuit, be sure to test at your maximum ambient temperature, and allow the FET to heat up with a normal amount of current before applying stress. You will probably find that there are some conditions (starting into a short circuit or low-value resistance, or a sudden heavy load) that cause damage to the FET if the timer is disabled.

    Thanks!

      Nathan

  • Hi Nathan,

    Thanks again for your quick response pointing out the pitfalls, I fully agree with your assessment. Output pulsing in overcurrent or short circuit situation is a problem in our application. There are multiple instruments on this output bus and some would generate false alarm.

    Is there any regulators/controllers that would do only Foldback during overcurrent/short circuit situation?

    Best Regards,

    Kali

  • Hi Kali,

        I don't know of any controllers that limit current without also limiting time. The problem is in protecting the FET by keeping it inside of its SOA. When the FET is current limiting it heats up, which can cause it to fail. If you impose a severe power limit (less current as Vds increases) you can lengthen the time, which may be sufficient for your needs, but ultimately you have to shut down the FET if the condition persists too long.

        I suggest that you play around with very large capacitor values on the TIMER pin to see if you can find a long duration time-out that also keeps the FET sate. You could also try tying the TIMER pin to GND through a small resistor to prevent it from ever timing out. The current limit will kick-in, and the foldback feature will throttle current as the output voltage droops. Again, though, remember that this is a very stressful condition for the FET, so you'll have to find a way to prevent overheating.

    Thanks!

      Nathan

  • Hi Nathan,

    Recently I bought a ADM1270RQ-EVALZ board. The timer capacitor C2 on this board is not connected to pin 10 of AD1270 as shown on the schematic. Instead, it's connected to D2 (not installed) which is not shown on the schematic. Do you know why that is? I am trying to run some experiment.

    Best Regards,

    Kali

  • Hi Kali,

        I apologize for the inconvenience. Your experience is unusual, so I will have to go investigate our demo board supply chain to see what happened. Please give me a few days to do that. While I am investigating, can you please post a photo of your board so I can get a better idea of the trouble? That would be helpful.

    Thanks!

       Nathan

  • Hi Nathan,

    Here is front and back view of the board.

    PDF

    Thank,

    Kali