Attached is a schematic of an ADP2384 on a board that I'm bringing up. There are several different switchers to support digital and analog loads -- all of which are being synchronized to a 1.2MHz clock generated by an FPGA. The individual sync clocks are phase shifted to prevent all the switchers from turning on their main power switch in unison.
This ADP2384 data sheet comment on p12... "rising edge of the switching waveform runs 180° out of phase to the rising edge of the external clock."... lead me to believe main power switch turn on event would be directly correlated with an edge.
The second attachment shows that the free-running ADP2384 does in fact synchronize to the external clock, but neither the turn on of the power switch or the sync. rectifier switch appears coincident with the rising or falling edge of the sync clock.
Is this behavior expected?
Is there a consistent delay between one of the sync clock edges and the main power switch on event?
Thanks for looking at this issue!
