we have implemented a design based on the LT3748 and LT8309 to supply 3A at 5V from ~48V input voltage (PoE application). The design works in principle, the measured output voltage is close to 5V with various loads.
A question occured while measuring the drain and gate waveforms on the secondary side. From the waveforms in the LT8309 manual or the LTspice simulation we would expect the following relations:
Schmetic based on the manufacturer 5V / 8A simulation, slightly adapted:
- load is approx 1.83A, output voltage: ~4.95V
- probe grounds are connected to the source of the secondary side MOSFET
- Channel 2 (blue): 5V output with 1uF in series and 50Ohm to GND (output ripple measurement)
- Channel 3 (pink): drain voltage
- Channel 4 (green): gate voltage
Comparing the measured waveforms to the expectations from the manual/simulation there are some differences:
1. Gate and drain are "synced", they show the same shape
2. The gate voltage is rather low (slightly above 1V)
3. There is an additional slope/pulse around the turn-on region of the gate/drain
Has somebody an idea what might be wrong (also mistakes in the measurement setup etc.)? Any help is appreciated.