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ADM1270 stability during Current limit Switch over

Hi,

We are planning to design a 28V fixed power supply with adjustable current limit setting using ISET pin of ADM1270 IC in discrete steps,need to know information on how stable the device will perform,during change over from one discrete current limit step to another on the go without power OFF .

Our concern is, when the switch over takes place,the ISET pin will be left floating for some momentary period,will this create problems. If so we would like know about some recommendations to be carried out for safely using ADM1270 IC in our design.

Regards,

Harish.S

  • Hi Harish,

                   I am the applications engineer for this product. It should be possible to adjust the current limit by changing the voltage on the ISET pin  as you describe. A small capacitor between the ISET pin and GND would help  reduce the glitches during the steps on the ISET pin. However,  I would need more detail on your application circuit to give a definitive answer. Can you share the portion of your schematic where you adjust the ISET voltage?

    Can you also explain in a bit more detail, the functionality you require? i.e. Do you need a continuous, adjustable current limit during normal operation, or do you need to part to limit current for a specific time and then switch off?

     

    Regards,

                  Donal

  • Hi Donald,

         Thanks for the reply, actually we are designing a bench top fixed voltage output supply with user configurable current limit. User will be allowed to change the current limit as required using a rotary switch available at the panel ,as the user turns the knob the  Resistor between  ISET and GND will be changed as per user current limit selection, it is possible that the user does it without powering down the system.

    During the period when the knob is turned to other positions,the bottom resistor will not be connected to ISET pin for a momentary period, we would like to know about the impact during this condition.

            Since we have not started drafting our Sch,attached a image of the application circuit from datasheet explaining the scheme that is planned for implementation, showing some of the discrete current limit steps planned.

    Regards,

    Harish.S

  • Hi Harish,

                   The way your circuit is designed means that when the lower resistor is disconnected, the voltage on ISET will be pulled up to 3.6 V (VCAP) momentarily. This means that the current limit will change to 10 A during this time as, when VISET > 2.65 V, the current limit threshold is reverts to it's default value of 50 mV.

    If this behavior is undesirable, you could do one of two things.

    1. change the rotary switch from a break-before-make to a make-before-break type so that you never have the lower side of the divider disconnected. this means that as you rotate the dial, the current limit would momentarily decrease as a pair of resistors are briefly connected in parallel.
    2. Modify the circuit so that the rotary switch changes the top resistor while the bottom resistor remains connected. When the top resistor is momentarily disconnected, the current limit would briefly change to 2 A .

    Please be aware that, the voltage on the FLB pin will modify current limit threshold. If you need to disable the foldback function, connect the FLB pin to VCAP.

    If you do not require reverse input voltage protection, you can eliminate Q2. Just leave the RFPG pin float and connect VIN directly to VCC/SENSE+.

    Regards,

                   Donal

  • Hi Donal,

       Thanks for the detailed explanation,we will go with your 1st option of using a make-before-break rotary switch in our design.

    Regards,

    Harish.S

     

     

  • HI Donal,

    Would like to know about the Vgs voltage that ADM1270 would support with IC supply voltage of 5V, this information is only available for the condition  60 V ≥ VCC≥ 14 V  in datasheet, even though IC's operational range is from  4 V to 60 V.

    Thanks & Regards,

    Harish.S

  • Hi Harish,

                   what this spec means is that for VCC > 14 V, but less than 60 V, the gate voltage will be clamped between 10 V

    and 14 V so  the the FET will never see a |VGS|  greater than this clamp value. If VCC is less than 14 V then the clamp is

    not active and GATE pin will be at the lowest possible voltage which is GND so that the VGS applied to the FET is equal to VCC.

    To answer your specific question, in the case of VCC = 5 V the VGS the FET will be ~5 V.

  • Hi Donal,

    It would be better if this is specifically mentioned in the datasheet in the next revision and thank you once again for the support.

    Regards,

    Harish.S