According to the distributors, there are two versions of the ADM691A. The ADM691A with a 35ms minimum reset timeout and the ADM691AA with a 140mS minimum reset timeout. I can't find any discussion in the data sheet that explains this. Can anyone point me in the right direction?
Thanks,
Keith
Hello, Keith.
Good day! We have 2 versions of ADM691 and they are listed below.
(1) ADM691: http://www.analog.com/media/en/technical-documentation/data-sheets/ADM690_691_692_693_694_695.pdf
(2) ADM691A: http://www.analog.com/media/en/technical-documentation/data-sheets/ADM691A_693A_800LM.pdf
ADM691 has 35ms reset timeout delay minimum (50ms typical).
ADM691A, on the other hand, has 140ms minimum (200ms typical).
Please see datasheet snapshots below. The respective ordering guide tables are on the right.
You may also want to check our power management solutions brochure.
Discussion for reset timeout delay is discussed on page 6 of ADM691 datasheet and on page 7 of ADM691A datasheet.
On power-up, the active-low RESET output will remain low for 50 ms after VCC rises above the appropriate reset threshold. This allows time for the power supply and microprocessor to stabilize.
In addition to active-low RESET output, the model also contains an active-high RESET output. This is the complement of active-low RESET and is intended for processors requiring an active-high RESET signal.
Regards,
Migs
Hello, Keith.
Good day! We have 2 versions of ADM691 and they are listed below.
(1) ADM691: http://www.analog.com/media/en/technical-documentation/data-sheets/ADM690_691_692_693_694_695.pdf
(2) ADM691A: http://www.analog.com/media/en/technical-documentation/data-sheets/ADM691A_693A_800LM.pdf
ADM691 has 35ms reset timeout delay minimum (50ms typical).
ADM691A, on the other hand, has 140ms minimum (200ms typical).
Please see datasheet snapshots below. The respective ordering guide tables are on the right.
You may also want to check our power management solutions brochure.
Discussion for reset timeout delay is discussed on page 6 of ADM691 datasheet and on page 7 of ADM691A datasheet.
On power-up, the active-low RESET output will remain low for 50 ms after VCC rises above the appropriate reset threshold. This allows time for the power supply and microprocessor to stabilize.
In addition to active-low RESET output, the model also contains an active-high RESET output. This is the complement of active-low RESET and is intended for processors requiring an active-high RESET signal.
Regards,
Migs
