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Solar LIPO charger with LT8490 not charging

Hi there

this is my first time here. Please be forbearing if i am doing anything wrong. :-) I am developing a solar charger to charge an 48V LIPO battery with a solar module using the LT8490. By now i am testing the (selfmade) board and it is not looking good. :-(

Testresults: The LT8490 seems to work as the status LED is blinking once (0.25s) every 3.5s. The fault LED is off. I tested the fault LED by using a 12V battery and then the fault LED showed an under-voltage fault as expected in the datasheet. The problem is, that the LT8490 is not charging although the status LED suggests stage 1 charging.

I can not measure any clock signal at the CLKOUT-pin.

Here are the facts:

Battery Voltage: 36.97V

SolarPanelVoltage: 35.36V (I am using a power supply for the tests as the solar panels have not arrived yet)

(MPP is supposed at 37V, open circuit is supposed at 48V)

INTVCC = 6.34V

SWEN = 0.72V

IMON_OUT = 0.7V (but there is no current. Actually imon_out is a pwm-signal from 0V-3.3V with a period of 27.4ms and a high-time of 6ms)

IMON_IN = 0.146V (i think this is normal as the imon_in circuit has an measurement offset of 7mV and there is no current flowing)

CSPOUT = 36.97V

CSNOUT = 36.97V

CSPIN = 35.36V

CSNIN = 35.36V

VBAT = 36.97V

VIN = 35.36V

TG1 = 0V

BG1 = 6.34V

TG2 = 0V

BG2 = 0V



BOOST2 = 5.92V

BOOST1 = 5.92V

FBIW = 2.53V


I am using 4 pieces of IPT007N06N FET's.

I am using 2 CMMR1U-02 TR diodes between GATEVCC and BOOST1/2

MODE is tied to an external 3.3V source.

The input feedback network is configured for 60V using the resistor / capacitor values from the datasheet.

The stage 2 voltage limit (Vs2) is set to 48V.

Charge current limit is set by a poti to 4.8A.

Input current is limited to 20A.

TempSense is not used. (11.5k and 10k resistors)

I attached the essential part of the schematic as the hole board contains way more than just this circuit. Please be aware that i canceled some parts from the schematic for the tests. You will know once you take a look at the schematic.


Please help me finding the bug. I am searching for days and cant find it. It is getting really depressing. I think i am making some very basic mistakes because of some misunderstanding. (My English could be much better) Thanks a lot for every helpful comment!

  • hi Patrick,

    sorry to hear about the difficulties with your prototype. usually the problem is a simple one but hard to figure out without a methodical approach.

    first, you need to change MOSFETs to much smaller devices. in buck-boost mode you have all MOSFETs switching and the current draw for gate drivers will exceed the available INTVCC current.

    I_INTVCC= 4 x Qg * frequency.

    at 6.3V gate drive you have 150nC per MOSFET and you are trying to run at 200kHz. that is 120mA.

    if you have more than 30mA current draw you probably have too large MOSFETs. and you should operate at 100 to 120kHz at this power level to keep switching losses down. you may need to increase inductance value. make sure the inductor does not saturate at 130mV/Rs, or 43A in your case.

    check gate resistors. if you have 0603 size standard thin film these resistors may be damaged by the power pulses. but they should be fine after changing to smaller MOSFETs.

    compare your schematic with the example in the data sheet. you seem to have trouble with IMONOUT signal, so you need to troubleshoot this circuit. remove the digital pot and add ordinary resistors, for troubleshooting.

    make sure your inductor current sense resistor R48 is not damaged. for initial troubleshooting I would reduce all current limits. for example, change from 2.5m to 10m.

    check that your 3.3V at LDO33 is normal and there is no unintentional overload.

    check all pins that have the power to block operation. SWEN is low. check SHDN, SS, VC. TEMPSNS, etc.

    you should check if the IMONOUT pin signal goes above 1.6V, because that would cause shutdown and restart (look at SS pin, if it does not go above 2V something like this is happening. but make sure SWEN is high, it can also block.

    when you test with a power supply instead of solar panel you should short VINR to gnd to disable the MPPT function.

    we have no simulation model for LT8490 but the power controller is a modified LT8705, so you could run a simulation of your power stage and try to understand what the different signals should look like.

    Layout errors can happen, also schematic errors, so it is important to check that schematic and layout match. sometimes the problem is too much solder on the exposed pad, so some pins are up in the air and not properly soldered.

  • Hi Tage

    Thank you so much for your fast and helpful comment. I did take a look at the simulation software of LT8705 and simulated my circuit with the following components using the LTpowerCAD II v2.5.2. (I attached the simulation file) As far as i can assess i think this should work better. What do you think about the new FET's? If you think the following actions would help, i will change the board as follows:

    - Rsens = 7mOhm

    - Rsensout = 10mOhm

    - FET = 4x IPT60R050G7 (4*68*10^-9*100000 = 27.2mA)

    - RT = 432kOm => 100kHz

    - Replace gate resistors

    - Replace dig. poti through ordinary resistor

    I checked the inductance: It saturates at 19A. I think this should work because i can afford to limit the current to less then 10A. Right?

    During simulation i mentioned that i have massiv iL-rippels if the output currents are less than 6A. Is that an issue?

    Once i changed the board i will try to restart it and do your suggested measurements. Then i will reply to you. Because i have to order some of the new components, this might take some days.

    Thanks a lot for your help.

  • regarding the saturation current, if you use 7 milliohm sense resistor for CSP-CSN input, the worst case peak current should be around 18A so if the inductor has 19A rating you are fine, especially if the inductor saturates softly. some ferrite cores have very sharp saturation. there are soft saturating cores that can take very large currents and still have some inductance. for example XAL1510 and similar. but instead they tend to have high core losses.

    100kHz is recommended for high power converters where switching losses will dominate. there is usually an optimal size for each MOSFET in the buckboost stage. if you use too large MOSFET you end up with unnecessary switching losses and high gate driver current draw. if the MOSFET is too small you of course end up with more conduction losses.

    the new part you  mention is not suitable. you need one that has Rdson specified at 6V. that is the only way you know it will work with 6.3V gate drive. a MOSFET that has Rdson specified at only 10V will have too high threshold voltage, and you will end up with failures because the MOSFET will not turn on fully when current is applied. the threshold voltage is specified at only 250uA current, so it cannot be used as a selection parameter. Rdson must be specified at 6V or 4.5V.

    if you already have a circuit board made for the large PG-HSOF-8 MOSFET package you could temporarily try IPT012N06N. it has 70nC gate charge at 6V (28mA at 100kHz in buckboost) and Rdson is typ 1.4mohm at 6V gate and 50A current. it is great overkill for your application, so in next board version you should use the SO8 footprint. if needed, use two parallel. even if you have a large package does not mean you can get the heat away from the MOSFET. you need a heatsink placed on the back side of the board, and hundreds of small via holes to transfer the heat from MOSFET through the board to the heatsink on the other side. between the board and the heatsink you need Bergquist gap pad material that works at low pressure (so you don't bend the board when tightening mounting screws).

    I will have to look at the simulation later.

  • Can you send the simulation file again, uncompressed. I could not open it.


  • Hi Tage

    Thanks a lot. I checked your proposed FET IPT012N06N. It would be a great choice but unfortunately its seems to be out of stock everywhere.

    I am not sure why my proposed FET (IPT60R050G7is not suitable:

    Rdson @ V_GS = 6V is specified in diagram 7. It is about 118mOhm at Id = 20A. But maybe i do not understand the datasheet right?

    Unfortunately there are not a lot of available FETs in PG-HSOF-8-package. I found two but they have all the same problem: Rdson is only in a diagram specified:

    IPT111N20NFD : 

    diagram 6 -> Rdson(V_GS = 6V) = 10mOhm  

    gate charge is typically 65nC, max. 87nC (table 6). However according to diagram 14 -> Gate Charge(V_GS = 6)  = 40nC


    Rdson is explicitly specified at 8V (5.2mOhm). According to diagram 6 the Rdson at 6V is <8mOhm.

    Gate charge is typically 69nC but could be up to 92nC (table 6). However according to diagram 14 it will be around 50nC at V_GS = 6V and id = 100A.

    Thanks a lot for the pdf's. There is one example which is very close to my application. I will check. Maybe i can find some major differences.

    I attached the datasheets of IPT60R050G7, IPT111N20NFD  and IPT059N15N3. Also i attached the simulation file.

    Thanks for your advice.

  • if the MOSFET does not have Rdson specified at 6V or 4.5V you cannot use it with LT8490. The figure you pointed to shows typical Rdson at certain gate voltage. but the 8490 will continue gate pulses even if driver voltage is below 5V. the danger is that if your prototype happens to work there is no guarantee that it will work under all operating conditions, and the next batch of MOSFETs may have a slightly lower gate threshold, or the operating temperature changes, or there is a current transient that causes the MOSFET to go into the active region where it is not saturated. this is a typical reason for failure when the MOSFET does not have Rdson spec at 6V or lower.

    can you send the simulation file uncompressed and in .ASC format, I cannot open the file.

  • Hi Tage

    i checked my circuit with your example and mentioned some differences. I attached your schematic and page 38 of the LT8490 as this contains an example i am referring often to. I highlighted the components in your schematic which i am referring to below. You have my schematic already.

    1. I have no L2

    I can't finde this inductance in the LT8490 datasheet. The example an page 38 doesen't show any such component. i assume it is not important.

    2. SW1/SW2 have an additional lowpassfilter in your example. (R15, C85 R25, C86)

    Same as at (1.)

    3. TG1 / TG2 have additional diodes (D18, D22, D27, D28) 

    I think these diodes are only important because you use two parallel FET's. So i don't need them.

    4. M2 and M3 have some additional resistor/diode network (R39, D23, R60, D24, R51, D25, R41, D26)

    I don't really get the point of these components but i assume it's the same as in (3.)

    5. CSP and CSN have an additional capacitor (C12) for filter purposes.

    It is not in the example of LT8490 example list but I see the point of this filter. Is it essential?

    6. ECON is left floating in my circuit.

    As i can accept "battery discharge when not charging" (datasheet page 30) i can left ECON floating?! 

    7. FBOW/SWEN/SWENO are connected to some additional components. 

    Same as in (6.)

    8. You have an additional resistor connected to CLKDET (R69)

    I did it as in the LT8490 example on page 38. I think this should be fine.

    9.You have an additional resistor connected to SYNC (R46)

    I think this resistor is not essential because it is never mentioned in the LT8490 datasheet.

    10. You have an additional resistor connected to IOW (R65)

    Should be fine according to page 18 of LT8490 datasheet.

    11. You have an additional resistor connected to AVDD (R86)

    I think this resistor is not needed according to example at page 38 of the LT8490 datasheet

    12. Generally we have different R- and C-values in our circuits.

    My Vin has a total capacity of 205uF

    Between Rsens1 and M1 i have 4.4uF

    Between M4 and Rsens2 i have 20uF

    My output capacity is about 170uF. I mentioned you use two small 2.2uF capacitors but i don't think this is a major issue.

    How is the VC resistor/capacitor network calculated? Maybe this is an issue?

  • ok i see the point. so i need to make an other board.... :-(

    actually it seems this webpage is compressing the simulation file. i never compressed anything. i attached an image of the simulation. if you have an email, i can send it to you directly.

  • hi Patrik, sorry for the delay but I am traveling this week and experienced issues with my work laptop. I don' t have access to all my data right now.

    1. when I created the DC2069A demo board I had to take into account all the different ways that it would be used, so there are some optional components that are not used. L2 was intended to reduce the ripple current caused by ripple on the input voltage as the power stage was switching. I wanted to avoid that noise currents would be injected into the signal ground area of the controller. bench testing later showed that it was not necessary to use L2, the trace impedance was enough. so L2 was replaced by a zero ohm resistor.

    2. I don't have the schematic in front of me, but I assume you are talking about the RC filters that are connected across the bottom MOSFETs. the reason for these snubbers are to dampen the ringing on the switch nodes. the parasitic inductance and capacitance will cause ringing when the MOSFETs are switching, and this creates EMI radiated noise. the RC snubber R is selected so the value is close to the characteristic impedance of the parasitic LC circuit. this dampens the ringing. the C is needed to block dc current in the R. it is selected so it has same or lower impedance at the ringing frequency as the value of R. I have a one page pdf that helps with selecting components in an RC snubber, will send it later. the RC snubbers are not needed for function but are often included in a final product to meet EMI test requirements.

    3. 4. the diodes across gate resistors are needed with some large MOSFETs when gate resistors are used, to avoid that the gate resistors slow down turn off. usually, we add gate resistors to slow down turn on of the active MOSFET and in some layouts to reduce ringing on gate drive traces. but it is important to make sure that the added impedance does not cause too slow turn off and shoot through (simultaneous conduction of top and bottom MOSFETs). so with some MOSFETs, gate diodes are used when it is necessary to use large value gate resistors. Gate resistors normally should not be larger than about 5ohms. 2ohm is more common.

    5. the RC filters on CSP and CSN are usually needed. R=10ohm, C=1nF...3.3nF. the capacitors must be placed close to the pins and connected to ground near the IC. the purpose is to filter the noise that appears across the sense resistor and the noise between sense resistor GND pad and signal GND of the IC. it is important to run both traces all the way from CSP and CSN pins to the sense resistor. do not ground the CSN pin near the IC. the 10ohm resistors can be placed anywhere along those two traces, but the most common placement in near the IC pins.

    6. ECON is an output and in many cases it is not used and can be left floating.

    7. SWENO is a digital output and must be connected to SWEN which is the enable pin. if it is allowed to float at startup, the power stage may start when it should not run, so you need a pulldown on SWEN.

    8. CLKOUT signal is only active when the controller is running, there is an RC lowpass filter that converts the squarewave to dc voltage that can be read by CLKDET which is an analog input. the RC filter is needed.

    9. if you are not using SYNC you can connect it to GND. if it is used to synchronize the power stage to an external clock, a pulldown resistor is connected from SYNC to GND to avoid that the pin floats which would cause failure. as the external clock is usually coming from some distance away, a small decoupling cap (10pF...100pF) is often placed close to the SYNC pin to avoid syncing to noise.

    10. IOW is open collector output that pulls down when full current limit is desired. if IOW is open circuit it means only one termination resistor is used on IMONOUT, so the current limit will be lower. this is used to limit charge current to about 20% of normal value, when battery voltage is very low. we do not want the battery to overheat while it is starting to charge in deep discharge mode.

    11. the resistor from LDO33 to AVDD is there to reduce ripple on AVDD (this supply voltage is used for analog to digital functions). the resistor can often be replaced by a short circuit, but it is good design practice to have a 1ohm resistor here. avoid larger value, as the voltage drop will affect accuracy.

    12. the input and output capacitors are not critical, but there are some things to consider. very important is to have ceramic capacitors connected to drains of M1 and M2. the ground pads of these ceramic caps should ideally be connected to ground pad of inductor sense resistor, at least the distance should not be large. you need a total capacitance of at least 2uF, but 10uF is better. the value is not critical but these caps are important. the electrolytic caps are often placed a bit away from the hot MOSFETs, so additional ceramic caps should be placed between the electrolytics and the input and output sense resistors. ceramic caps take heat up to +125C without damage, electrolytics get short lived if operating at hot temperature, even if they would be selected to operate at up to +125C. Most common temperature rating for the electrolytic input and output caps is +105C. if traditional electrolytic caps are used they must be able to take the rms ripple current. today we often use hybrid capacitors as they are smaller. but sometimes you want more capacitance than those hybrids give, and you use large size aluminum electrolytics intended for switching applications (low ESR, high RMS rating). larger capacitance on input voltage gives better low power mode performance, larger value on output gives less overshoot at startup with no battery, or if battery is removed while charge current is flowing. I think your values are good.

    without going into pages of explanation, use compensation component values on VC pin as shown in examples. the capacitor from VC to GND is normally about 220pF. its purpose is mainly to reduce noise. the R and C series combination is what compensates the control loop. put a probe on this VC pin to check that there is not a sinewave signal, it should be dc with some variation with current and input voltage. the C is often at least ten times larger than the small cap (2.2nF or larger if the single cap is 220pF. a good starting value is 3.3nF) and the R is used to select crossover frequency. lower value means lower control loop reactions, higher value means faster control but potential for unstable loop. R is usually in the range 5k to 50k. 10k is a good starting value.